[AArch64] Implement CRC32 ACLE intrinsics.
* config.gcc (aarch64*-*-*): Add arm_acle.h to extra headers. * Makefile.in (TEXI_GCC_FILES): Add aarch64-acle-intrinsics.texi to dependencies. * config/aarch64/aarch64-builtins.c (AARCH64_CRC32_BUILTINS): Define. (aarch64_crc_builtin_datum): New struct. (aarch64_crc_builtin_data): New. (aarch64_init_crc32_builtins): New function. (aarch64_init_builtins): Initialise CRC32 builtins when appropriate. (aarch64_crc32_expand_builtin): New. (aarch64_expand_builtin): Add CRC32 builtin expansion case. * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_FEATURE_CRC32 when appropriate. (TARGET_CRC32): Define. * config/aarch64/aarch64.md (UNSPEC_CRC32B, UNSPEC_CRC32H, UNSPEC_CRC32W, UNSPEC_CRC32X, UNSPEC_CRC32CB, UNSPEC_CRC32CH, UNSPEC_CRC32CW, UNSPEC_CRC32CX): New unspec values. (aarch64_<crc_variant>): New pattern. * config/aarch64/arm_acle.h: New file. * config/aarch64/iterators.md (CRC): New int iterator. (crc_variant, crc_mode): New int attributes. * doc/aarch64-acle-intrinsics.texi: New file. * doc/extend.texi (aarch64): Document aarch64 ACLE intrinsics. Include aarch64-acle-intrinsics.texi. From-SVN: r211440
This commit is contained in:
Kyrylo Tkachov
Kyrylo Tkachov
parent
e1377713ce
commit
5d357f260c
10 changed files with 317 additions and 3 deletions
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@ -1,3 +1,29 @@
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2014-06-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config.gcc (aarch64*-*-*): Add arm_acle.h to extra headers.
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* Makefile.in (TEXI_GCC_FILES): Add aarch64-acle-intrinsics.texi to
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dependencies.
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* config/aarch64/aarch64-builtins.c (AARCH64_CRC32_BUILTINS): Define.
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(aarch64_crc_builtin_datum): New struct.
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(aarch64_crc_builtin_data): New.
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(aarch64_init_crc32_builtins): New function.
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(aarch64_init_builtins): Initialise CRC32 builtins when appropriate.
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(aarch64_crc32_expand_builtin): New.
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(aarch64_expand_builtin): Add CRC32 builtin expansion case.
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* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define
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__ARM_FEATURE_CRC32 when appropriate.
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(TARGET_CRC32): Define.
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* config/aarch64/aarch64.md (UNSPEC_CRC32B, UNSPEC_CRC32H,
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UNSPEC_CRC32W, UNSPEC_CRC32X, UNSPEC_CRC32CB, UNSPEC_CRC32CH,
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UNSPEC_CRC32CW, UNSPEC_CRC32CX): New unspec values.
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(aarch64_<crc_variant>): New pattern.
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* config/aarch64/arm_acle.h: New file.
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* config/aarch64/iterators.md (CRC): New int iterator.
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(crc_variant, crc_mode): New int attributes.
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* doc/aarch64-acle-intrinsics.texi: New file.
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* doc/extend.texi (aarch64): Document aarch64 ACLE intrinsics.
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Include aarch64-acle-intrinsics.texi.
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2014-06-11 Evgeny Stupachenko <evstupac@gmail.com>
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* tree-vect-data-refs.c (vect_grouped_store_supported): New
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@ -2801,7 +2801,7 @@ TEXI_GCC_FILES = gcc.texi gcc-common.texi gcc-vers.texi frontends.texi \
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contribute.texi compat.texi funding.texi gnu.texi gpl_v3.texi \
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fdl.texi contrib.texi cppenv.texi cppopts.texi avr-mmcu.texi \
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implement-c.texi implement-cxx.texi arm-neon-intrinsics.texi \
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arm-acle-intrinsics.texi
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arm-acle-intrinsics.texi aarch64-acle-intrinsics.texi
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# we explicitly use $(srcdir)/doc/tm.texi here to avoid confusion with
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# the generated tm.texi; the latter might have a more recent timestamp,
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@ -302,7 +302,7 @@ m32c*-*-*)
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;;
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aarch64*-*-*)
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cpu_type=aarch64
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extra_headers="arm_neon.h"
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extra_headers="arm_neon.h arm_acle.h"
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extra_objs="aarch64-builtins.o aarch-common.o"
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target_has_targetm_common=yes
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;;
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@ -411,6 +411,28 @@ static aarch64_simd_builtin_datum aarch64_simd_builtin_data[] = {
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#include "aarch64-simd-builtins.def"
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};
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/* There's only 8 CRC32 builtins. Probably not worth their own .def file. */
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#define AARCH64_CRC32_BUILTINS \
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CRC32_BUILTIN (crc32b, QI) \
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CRC32_BUILTIN (crc32h, HI) \
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CRC32_BUILTIN (crc32w, SI) \
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CRC32_BUILTIN (crc32x, DI) \
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CRC32_BUILTIN (crc32cb, QI) \
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CRC32_BUILTIN (crc32ch, HI) \
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CRC32_BUILTIN (crc32cw, SI) \
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CRC32_BUILTIN (crc32cx, DI)
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typedef struct
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{
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const char *name;
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enum machine_mode mode;
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const enum insn_code icode;
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unsigned int fcode;
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} aarch64_crc_builtin_datum;
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#define CRC32_BUILTIN(N, M) \
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AARCH64_BUILTIN_##N,
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#undef VAR1
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#define VAR1(T, N, MAP, A) \
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AARCH64_SIMD_BUILTIN_##T##_##N##A,
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@ -428,9 +450,22 @@ enum aarch64_builtins
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#include "aarch64-simd-builtins.def"
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AARCH64_SIMD_BUILTIN_MAX = AARCH64_SIMD_BUILTIN_BASE
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+ ARRAY_SIZE (aarch64_simd_builtin_data),
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AARCH64_CRC32_BUILTIN_BASE,
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AARCH64_CRC32_BUILTINS
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AARCH64_CRC32_BUILTIN_MAX,
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AARCH64_BUILTIN_MAX
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};
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#undef CRC32_BUILTIN
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#define CRC32_BUILTIN(N, M) \
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{"__builtin_aarch64_"#N, M##mode, CODE_FOR_aarch64_##N, AARCH64_BUILTIN_##N},
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static aarch64_crc_builtin_datum aarch64_crc_builtin_data[] = {
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AARCH64_CRC32_BUILTINS
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};
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#undef CRC32_BUILTIN
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static GTY(()) tree aarch64_builtin_decls[AARCH64_BUILTIN_MAX];
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#define NUM_DREG_TYPES 6
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@ -802,6 +837,24 @@ aarch64_init_simd_builtins (void)
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}
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}
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static void
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aarch64_init_crc32_builtins ()
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{
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tree usi_type = aarch64_build_unsigned_type (SImode);
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unsigned int i = 0;
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for (i = 0; i < ARRAY_SIZE (aarch64_crc_builtin_data); ++i)
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{
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aarch64_crc_builtin_datum* d = &aarch64_crc_builtin_data[i];
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tree argtype = aarch64_build_unsigned_type (d->mode);
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tree ftype = build_function_type_list (usi_type, usi_type, argtype, NULL_TREE);
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tree fndecl = add_builtin_function (d->name, ftype, d->fcode,
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BUILT_IN_MD, NULL, NULL_TREE);
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aarch64_builtin_decls[d->fcode] = fndecl;
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}
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}
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void
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aarch64_init_builtins (void)
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{
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@ -825,6 +878,8 @@ aarch64_init_builtins (void)
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if (TARGET_SIMD)
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aarch64_init_simd_builtins ();
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if (TARGET_CRC32)
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aarch64_init_crc32_builtins ();
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}
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tree
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@ -1024,6 +1079,41 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
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SIMD_ARG_STOP);
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}
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rtx
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aarch64_crc32_expand_builtin (int fcode, tree exp, rtx target)
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{
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rtx pat;
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aarch64_crc_builtin_datum *d
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= &aarch64_crc_builtin_data[fcode - (AARCH64_CRC32_BUILTIN_BASE + 1)];
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enum insn_code icode = d->icode;
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tree arg0 = CALL_EXPR_ARG (exp, 0);
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tree arg1 = CALL_EXPR_ARG (exp, 1);
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rtx op0 = expand_normal (arg0);
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rtx op1 = expand_normal (arg1);
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enum machine_mode tmode = insn_data[icode].operand[0].mode;
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enum machine_mode mode0 = insn_data[icode].operand[1].mode;
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enum machine_mode mode1 = insn_data[icode].operand[2].mode;
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if (! target
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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target = gen_reg_rtx (tmode);
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gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
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&& (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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pat = GEN_FCN (icode) (target, op0, op1);
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if (! pat)
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return 0;
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emit_insn (pat);
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return target;
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}
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/* Expand an expression EXP that calls a built-in function,
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with result going to TARGET if that's convenient. */
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rtx
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@ -1066,8 +1156,10 @@ aarch64_expand_builtin (tree exp,
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return target;
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}
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if (fcode >= AARCH64_SIMD_BUILTIN_BASE)
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if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX)
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return aarch64_simd_expand_builtin (fcode, exp, target);
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else if (fcode >= AARCH64_CRC32_BUILTIN_BASE && fcode <= AARCH64_CRC32_BUILTIN_MAX)
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return aarch64_crc32_expand_builtin (fcode, exp, target);
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return NULL_RTX;
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}
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@ -35,6 +35,9 @@
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if (TARGET_SIMD) \
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builtin_define ("__ARM_NEON"); \
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\
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if (TARGET_CRC32) \
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builtin_define ("__ARM_FEATURE_CRC32"); \
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\
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switch (aarch64_cmodel) \
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{ \
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case AARCH64_CMODEL_TINY: \
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@ -188,6 +191,9 @@ extern unsigned long aarch64_tune_flags;
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/* Crypto is an optional extension to AdvSIMD. */
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#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
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/* CRC instructions that can be enabled through +crc arch extension. */
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#define TARGET_CRC32 (AARCH64_ISA_CRC)
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/* Standard register usage. */
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/* 31 64-bit general purpose registers R0-R30:
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@ -68,6 +68,14 @@
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(define_c_enum "unspec" [
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UNSPEC_CASESI
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UNSPEC_CLS
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UNSPEC_CRC32B
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UNSPEC_CRC32CB
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UNSPEC_CRC32CH
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UNSPEC_CRC32CW
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UNSPEC_CRC32CX
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UNSPEC_CRC32H
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UNSPEC_CRC32W
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UNSPEC_CRC32X
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UNSPEC_FRECPE
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UNSPEC_FRECPS
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UNSPEC_FRECPX
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@ -2481,6 +2489,23 @@
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}
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)
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;; CRC32 instructions.
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(define_insn "aarch64_<crc_variant>"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:SI 1 "register_operand" "r")
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(match_operand:<crc_mode> 2 "register_operand" "r")]
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CRC))]
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"TARGET_CRC32"
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{
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if (GET_MODE_BITSIZE (GET_MODE (operands[2])) >= 64)
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return "<crc_variant>\\t%w0, %w1, %x2";
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else
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return "<crc_variant>\\t%w0, %w1, %w2";
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}
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[(set_attr "type" "crc")]
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)
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(define_insn "*csinc2<mode>_insn"
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[(set (match_operand:GPI 0 "register_operand" "=r")
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(plus:GPI (match_operator:GPI 2 "aarch64_comparison_operator"
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90
gcc/config/aarch64/arm_acle.h
Normal file
90
gcc/config/aarch64/arm_acle.h
Normal file
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@ -0,0 +1,90 @@
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/* AArch64 Non-NEON ACLE intrinsics include file.
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Copyright (C) 2014 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _GCC_ARM_ACLE_H
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#define _GCC_ARM_ACLE_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __ARM_FEATURE_CRC32
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32b (uint32_t __a, uint8_t __b)
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{
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return __builtin_aarch64_crc32b (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32cb (uint32_t __a, uint8_t __b)
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{
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return __builtin_aarch64_crc32cb (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32ch (uint32_t __a, uint16_t __b)
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{
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return __builtin_aarch64_crc32ch (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32cw (uint32_t __a, uint32_t __b)
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{
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return __builtin_aarch64_crc32cw (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32cd (uint32_t __a, uint64_t __b)
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{
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return __builtin_aarch64_crc32cx (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32h (uint32_t __a, uint16_t __b)
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{
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return __builtin_aarch64_crc32h (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32w (uint32_t __a, uint32_t __b)
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{
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return __builtin_aarch64_crc32w (__a, __b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32d (uint32_t __a, uint64_t __b)
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{
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return __builtin_aarch64_crc32x (__a, __b);
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -910,6 +910,10 @@
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(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
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(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
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UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
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UNSPEC_CRC32CW UNSPEC_CRC32CX])
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(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
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(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
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@ -1038,6 +1042,16 @@
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(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
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(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
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(UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
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(UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
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(UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
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(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
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(UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
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(UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
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(UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
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(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
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(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
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55
gcc/doc/aarch64-acle-intrinsics.texi
Normal file
55
gcc/doc/aarch64-acle-intrinsics.texi
Normal file
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@ -0,0 +1,55 @@
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@c Copyright (C) 2014 Free Software Foundation, Inc.
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@c This is part of the GCC manual.
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@c For copying conditions, see the file gcc.texi.
|
||||
|
||||
@subsubsection CRC32 intrinsics
|
||||
|
||||
These intrinsics are available when the CRC32 architecture extension is
|
||||
specified, e.g. when the @option{-march=armv8-a+crc} switch is used, or when
|
||||
the target processor specified with @option{-mcpu} supports it.
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32_t __crc32b (uint32_t, uint8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{crc32b @var{w0}, @var{w1}, @var{w2}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32_t __crc32h (uint32_t, uint16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{crc32h @var{w0}, @var{w1}, @var{w2}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32_t __crc32w (uint32_t, uint32_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{crc32w @var{w0}, @var{w1}, @var{w2}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32_t __crc32d (uint32_t, uint64_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{crc32x @var{w0}, @var{w1}, @var{x2}}
|
||||
@end itemize
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32_t __crc32cb (uint32_t, uint8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{crc32cb @var{w0}, @var{w1}, @var{w2}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32_t __crc32ch (uint32_t, uint16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{crc32ch @var{w0}, @var{w1}, @var{w2}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32_t __crc32cw (uint32_t, uint32_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{crc32cw @var{w0}, @var{w1}, @var{w2}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32_t __crc32cd (uint32_t, uint64_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{crc32cx @var{w0}, @var{w1}, @var{x2}}
|
||||
@end itemize
|
||||
|
|
@ -9697,6 +9697,7 @@ instructions, but allow the compiler to schedule those calls.
|
|||
|
||||
@menu
|
||||
* AArch64 Built-in Functions::
|
||||
* AArch64 intrinsics::
|
||||
* Alpha Built-in Functions::
|
||||
* Altera Nios II Built-in Functions::
|
||||
* ARC Built-in Functions::
|
||||
|
|
@ -9742,6 +9743,11 @@ unsigned int __builtin_aarch64_get_fpsr ()
|
|||
void __builtin_aarch64_set_fpsr (unsigned int)
|
||||
@end smallexample
|
||||
|
||||
@node AArch64 intrinsics
|
||||
@subsection ACLE Intrinsics for AArch64
|
||||
|
||||
@include aarch64-acle-intrinsics.texi
|
||||
|
||||
@node Alpha Built-in Functions
|
||||
@subsection Alpha Built-in Functions
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue