From 5cb55204f2d2b4e1c10d9baba320f6be7d5f6631 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Thu, 15 Jul 2010 02:07:53 +0000 Subject: [PATCH] cortex-a8.md (cortex_a8_load_store_2): Reserve cortex_a8_issue_ls. * config/arm/cortex-a8.md (cortex_a8_load_store_2): Reserve cortex_a8_issue_ls. From-SVN: r162201 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/cortex-a8.md | 10 ++++------ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 29db69c6a3d..3e96698dbf5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2010-07-15 Jie Zhang + + * config/arm/cortex-a8.md (cortex_a8_load_store_2): Reserve + cortex_a8_issue_ls. + 2010-07-15 Dave Korn * config/i386/cygwin.h (LIBGCJ_SONAME): Update. diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index 156959fa43f..8ac754ebc28 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -47,17 +47,15 @@ "(cortex_a8_alu0+cortex_a8_issue_ls)|\ (cortex_a8_alu1+cortex_a8_issue_ls)") -;; ...and in the case of two micro-ops. We don't need to reserve -;; cortex_a8_issue_ls here because dual issue is altogether forbidden +;; ...and in the case of two micro-ops. Dual issue is altogether forbidden ;; during the issue cycle of the first micro-op. (Instead of modelling ;; a separate issue unit, we instead reserve alu0 and alu1 to ;; prevent any other instructions from being issued upon that first cycle.) ;; Even though the load/store pipeline is usually available in either -;; ALU pipe, multi-cycle instructions always issue in pipeline 0. This -;; reservation is therefore the same as cortex_a8_multiply_2 below. +;; ALU pipe, multi-cycle instructions always issue in pipeline 0. (define_reservation "cortex_a8_load_store_2" - "cortex_a8_alu0+cortex_a8_alu1,\ - cortex_a8_alu0") + "cortex_a8_alu0+cortex_a8_alu1+cortex_a8_issue_ls,\ + cortex_a8_alu0+cortex_a8_issue_ls") ;; The flow of a single-cycle multiplication. (define_reservation "cortex_a8_multiply"