alpha.h (HARD_REGNO_MODE_OK): Disallow SImode in FP regs.
* alpha.h (HARD_REGNO_MODE_OK): Disallow SImode in FP regs.
* alpha.md (UNSPEC_NT_LDA): Remove.
(UNSPEC_CVTLQ, cvtlq): New.
(extendsidi2_1): Rename from extendsidi2_nofix; remove f/f.
(extendsidi2_fix): Remove.
(extendsidi2 splitter): Use cvtlq.
(extendsidi2 fp peepholes): Remove.
(cvtql): Use SFmode instead of SImode.
(fix_trunc?fsi): Update to match.
(floatsisf2_ieee, floatsisf2, floatsidf2_ieee, floatsidf2): New.
(movsi): Rename from movsi_nofix, remove f alternatives.
(movsi_nt_vms): Similarly.
(movsi_fix, movsi_nt_vms_fix): Remove.
(nt_lda): Remove.
* alpha.c (alpha_expand_prologue): Use adddi3, not nt_lda.
From-SVN: r76145
This commit is contained in:
Richard Henderson
Richard Henderson
parent
9b0436b739
commit
5c9948f4e8
4 changed files with 138 additions and 140 deletions
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@ -1,3 +1,21 @@
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2004-01-19 Richard Henderson <rth@redhat.com>
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* alpha.h (HARD_REGNO_MODE_OK): Disallow SImode in FP regs.
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* alpha.md (UNSPEC_NT_LDA): Remove.
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(UNSPEC_CVTLQ, cvtlq): New.
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(extendsidi2_1): Rename from extendsidi2_nofix; remove f/f.
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(extendsidi2_fix): Remove.
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(extendsidi2 splitter): Use cvtlq.
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(extendsidi2 fp peepholes): Remove.
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(cvtql): Use SFmode instead of SImode.
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(fix_trunc?fsi): Update to match.
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(floatsisf2_ieee, floatsisf2, floatsidf2_ieee, floatsidf2): New.
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(movsi): Rename from movsi_nofix, remove f alternatives.
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(movsi_nt_vms): Similarly.
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(movsi_fix, movsi_nt_vms_fix): Remove.
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(nt_lda): Remove.
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* alpha.c (alpha_expand_prologue): Use adddi3, not nt_lda.
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2004-01-19 Jan Hubicka <jh@suse.cz>
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* cgraph.c (cgraph_remove_node): Fix removal from linked list.
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@ -7147,15 +7147,14 @@ alpha_expand_prologue (void)
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and subtract it to sp.
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Yes, that's correct -- we have to reload the whole constant
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into a temporary via ldah+lda then subtract from sp. To
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ensure we get ldah+lda, we use a special pattern. */
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into a temporary via ldah+lda then subtract from sp. */
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HOST_WIDE_INT lo, hi;
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lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
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hi = frame_size - lo;
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emit_move_insn (ptr, GEN_INT (hi));
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emit_insn (gen_nt_lda (ptr, GEN_INT (lo)));
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emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
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seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
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ptr));
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}
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@ -614,12 +614,11 @@ extern const char *alpha_tls_size_string; /* For -mtls-size= */
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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On Alpha, the integer registers can hold any mode. The floating-point
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registers can hold 32-bit and 64-bit integers as well, but not 16-bit
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or 8-bit values. */
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registers can hold 64-bit integers as well, but not smaller values. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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((REGNO) >= 32 && (REGNO) <= 62 \
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? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
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? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \
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: 1)
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/* Value is 1 if MODE is a supported vector mode. */
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@ -30,7 +30,7 @@
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(UNSPEC_INSXH 2)
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(UNSPEC_MSKXH 3)
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(UNSPEC_CVTQL 4)
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(UNSPEC_NT_LDA 5)
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(UNSPEC_CVTLQ 5)
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(UNSPEC_UMK_LAUM 6)
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(UNSPEC_UMK_LALM 7)
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(UNSPEC_UMK_LAL 8)
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@ -185,41 +185,36 @@
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""
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"")
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(define_insn "*extendsidi2_nofix"
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[(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
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(define_insn "*cvtlq"
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[(set (match_operand:DI 0 "register_operand" "=f")
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(unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
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UNSPEC_CVTLQ))]
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""
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"cvtlq %1,%0"
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[(set_attr "type" "fadd")])
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(define_insn "*extendsidi2_1"
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[(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
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(sign_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
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"! TARGET_FIX"
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(match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
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""
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"@
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addl $31,%1,%0
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ldl %0,%1
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cvtlq %1,%0
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lds %0,%1\;cvtlq %0,%0"
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[(set_attr "type" "iadd,ild,fadd,fld")
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(set_attr "length" "*,*,*,8")])
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[(set_attr "type" "iadd,ild,fld")
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(set_attr "length" "*,*,8")])
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(define_insn "*extendsidi2_fix"
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[(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
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(sign_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
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"TARGET_FIX"
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"@
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addl $31,%1,%0
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ldl %0,%1
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ftois %1,%0
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cvtlq %1,%0
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lds %0,%1\;cvtlq %0,%0"
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[(set_attr "type" "iadd,ild,ftoi,fadd,fld")
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(set_attr "length" "*,*,*,*,8")])
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;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
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(define_split
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[(set (match_operand:DI 0 "hard_fp_register_operand" "")
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(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
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"reload_completed"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (sign_extend:DI (match_dup 2)))]
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"operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
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(set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
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{
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operands[1] = adjust_address (operands[1], SFmode, 0);
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operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
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})
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;; Optimize sign-extension of SImode loads. This shows up in the wake of
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;; reload when converting fp->int.
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@ -235,28 +230,6 @@
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(sign_extend:DI (match_dup 1)))]
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"")
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(define_peephole2
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[(set (match_operand:SI 0 "hard_int_register_operand" "")
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(match_operand:SI 1 "hard_fp_register_operand" ""))
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(set (match_operand:DI 2 "hard_int_register_operand" "")
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(sign_extend:DI (match_dup 0)))]
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"TARGET_FIX
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&& (true_regnum (operands[0]) == true_regnum (operands[2])
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|| peep2_reg_dead_p (2, operands[0]))"
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[(set (match_dup 2)
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(sign_extend:DI (match_dup 1)))]
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"")
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(define_peephole2
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[(set (match_operand:DI 0 "hard_fp_register_operand" "")
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(sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
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(set (match_operand:DI 2 "hard_int_register_operand" "")
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(match_dup 0))]
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"TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
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[(set (match_dup 2)
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(sign_extend:DI (match_dup 1)))]
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"")
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;; Don't say we have addsi3 if optimizing. This generates better code. We
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;; have the anonymous addsi3 pattern below in case combine wants to make it.
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(define_expand "addsi3"
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@ -2334,8 +2307,8 @@
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;; processing, it is cheaper to do the truncation in the int regs.
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(define_insn "*cvtql"
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[(set (match_operand:SI 0 "register_operand" "=f")
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(unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")]
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[(set (match_operand:SF 0 "register_operand" "=f")
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(unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
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UNSPEC_CVTQL))]
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"TARGET_FP"
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"cvtql%/ %R1,%0"
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@ -2349,14 +2322,16 @@
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(match_operator:DI 4 "fix_operator"
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[(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
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(clobber (match_scratch:DI 2 "=&f"))
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(clobber (match_scratch:SI 3 "=&f"))]
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(clobber (match_scratch:SF 3 "=&f"))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
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(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 3))]
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""
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(set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 5) (match_dup 3))]
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{
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operands[5] = adjust_address (operands[0], SFmode, 0);
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}
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")])
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@ -2370,10 +2345,12 @@
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
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(set (match_dup 4) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 4))]
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;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
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"operands[4] = gen_rtx_REG (SImode, REGNO (operands[2]));"
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(set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 5) (match_dup 4))]
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{
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operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
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operands[5] = adjust_address (operands[0], SFmode, 0);
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}
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")])
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@ -2420,14 +2397,16 @@
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[(float_extend:DF
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(match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
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(clobber (match_scratch:DI 2 "=&f"))
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(clobber (match_scratch:SI 3 "=&f"))]
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(clobber (match_scratch:SF 3 "=&f"))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
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(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 3))]
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""
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(set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 4) (match_dup 3))]
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{
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operands[4] = adjust_address (operands[0], SFmode, 0);
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}
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")])
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@ -2442,10 +2421,12 @@
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
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(set (match_dup 4) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 0) (match_dup 4))]
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;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
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"operands[4] = gen_rtx_REG (SImode, REGNO (operands[2]));"
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(set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
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(set (match_dup 5) (match_dup 4))]
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{
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operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
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operands[5] = adjust_address (operands[0], SFmode, 0);
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}
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[(set_attr "type" "fadd")
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(set_attr "trap" "yes")])
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@ -2516,6 +2497,35 @@
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "sui")])
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(define_insn_and_split "*floatsisf2_ieee"
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[(set (match_operand:SF 0 "register_operand" "=&f")
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(float:SF (match_operand:SI 1 "memory_operand" "m")))
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(clobber (match_scratch:DI 2 "=&f"))
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(clobber (match_scratch:SF 3 "=&f"))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"#"
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"&& reload_completed"
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[(set (match_dup 3) (match_dup 1))
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(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
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(set (match_dup 0) (float:SF (match_dup 2)))]
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{
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operands[1] = adjust_address (operands[1], SFmode, 0);
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})
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(define_insn_and_split "*floatsisf2"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(float:SF (match_operand:SI 1 "memory_operand" "m")))]
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"TARGET_FP"
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"#"
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"&& reload_completed"
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[(set (match_dup 0) (match_dup 1))
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(set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
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(set (match_dup 0) (float:SF (match_dup 2)))]
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{
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operands[1] = adjust_address (operands[1], SFmode, 0);
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operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
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})
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(define_insn "*floatdidf_ieee"
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[(set (match_operand:DF 0 "register_operand" "=&f")
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(float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
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@ -2536,6 +2546,36 @@
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(set_attr "round_suffix" "normal")
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(set_attr "trap_suffix" "sui")])
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(define_insn_and_split "*floatsidf2_ieee"
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[(set (match_operand:DF 0 "register_operand" "=&f")
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(float:DF (match_operand:SI 1 "memory_operand" "m")))
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(clobber (match_scratch:DI 2 "=&f"))
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(clobber (match_scratch:SF 3 "=&f"))]
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"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
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"#"
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"&& reload_completed"
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[(set (match_dup 3) (match_dup 1))
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(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
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(set (match_dup 0) (float:DF (match_dup 2)))]
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{
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operands[1] = adjust_address (operands[1], SFmode, 0);
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})
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(define_insn_and_split "*floatsidf2"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(float:DF (match_operand:SI 1 "memory_operand" "m")))]
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"TARGET_FP"
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"#"
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"&& reload_completed"
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[(set (match_dup 3) (match_dup 1))
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(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
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(set (match_dup 0) (float:DF (match_dup 2)))]
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{
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operands[1] = adjust_address (operands[1], SFmode, 0);
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operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
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operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
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})
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(define_expand "floatditf2"
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[(use (match_operand:TF 0 "register_operand" ""))
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(use (match_operand:DI 1 "general_operand" ""))]
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@ -5166,10 +5206,10 @@
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operands[1] = force_reg (TFmode, operands[1]);
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})
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(define_insn "*movsi_nofix"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
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(match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
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"(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
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(define_insn "*movsi"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m")
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(match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ"))]
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"(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
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&& (register_operand (operands[0], SImode)
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|| reg_or_0_operand (operands[1], SImode))"
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||||
"@
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||||
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|
@ -5177,36 +5217,13 @@
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lda %0,%1($31)
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ldah %0,%h1($31)
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ldl %0,%1
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stl %r1,%0
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cpys %R1,%R1,%0
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ld%, %0,%1
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st%, %R1,%0"
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[(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
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stl %r1,%0"
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[(set_attr "type" "ilog,iadd,iadd,ild,ist")])
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(define_insn "*movsi_fix"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
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(match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
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"TARGET_ABI_OSF && TARGET_FIX
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&& (register_operand (operands[0], SImode)
|
||||
|| reg_or_0_operand (operands[1], SImode))"
|
||||
"@
|
||||
bis $31,%r1,%0
|
||||
lda %0,%1($31)
|
||||
ldah %0,%h1($31)
|
||||
ldl %0,%1
|
||||
stl %r1,%0
|
||||
cpys %R1,%R1,%0
|
||||
ld%, %0,%1
|
||||
st%, %R1,%0
|
||||
ftois %1,%0
|
||||
itofs %1,%0"
|
||||
[(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
|
||||
|
||||
(define_insn "*movsi_nt_vms_nofix"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
|
||||
(match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
|
||||
(define_insn "*movsi_nt_vms"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
|
||||
(match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ"))]
|
||||
"(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
|
||||
&& !TARGET_FIX
|
||||
&& (register_operand (operands[0], SImode)
|
||||
|| reg_or_0_operand (operands[1], SImode))"
|
||||
"@
|
||||
|
|
@ -5215,32 +5232,8 @@
|
|||
ldah %0,%h1
|
||||
lda %0,%1
|
||||
ldl %0,%1
|
||||
stl %r1,%0
|
||||
cpys %R1,%R1,%0
|
||||
ld%, %0,%1
|
||||
st%, %R1,%0"
|
||||
[(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
|
||||
|
||||
(define_insn "*movsi_nt_vms_fix"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
|
||||
(match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
|
||||
"(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
|
||||
&& TARGET_FIX
|
||||
&& (register_operand (operands[0], SImode)
|
||||
|| reg_or_0_operand (operands[1], SImode))"
|
||||
"@
|
||||
bis $31,%1,%0
|
||||
lda %0,%1
|
||||
ldah %0,%h1
|
||||
lda %0,%1
|
||||
ldl %0,%1
|
||||
stl %r1,%0
|
||||
cpys %R1,%R1,%0
|
||||
ld%, %0,%1
|
||||
st%, %R1,%0
|
||||
ftois %1,%0
|
||||
itofs %1,%0"
|
||||
[(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
|
||||
stl %r1,%0"
|
||||
[(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist")])
|
||||
|
||||
(define_insn "*movhi_nobwx"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,r")
|
||||
|
|
@ -6901,17 +6894,6 @@
|
|||
DONE;
|
||||
})
|
||||
|
||||
;; In creating a large stack frame, NT _must_ use ldah+lda to load
|
||||
;; the frame size into a register. We use this pattern to ensure
|
||||
;; we get lda instead of addq.
|
||||
(define_insn "nt_lda"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unspec:DI [(match_dup 0)
|
||||
(match_operand:DI 1 "const_int_operand" "n")]
|
||||
UNSPEC_NT_LDA))]
|
||||
""
|
||||
"lda %0,%1(%0)")
|
||||
|
||||
(define_expand "builtin_longjmp"
|
||||
[(use (match_operand:DI 0 "register_operand" "r"))]
|
||||
"TARGET_ABI_OSF"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue