Enable more optimization for 32-bit/64-bit shrd/shld with imm shift count.
This patch doens't handle variable count since it require 5 insns to be combined to get wanted pattern, but current pass_combine only supports at most 4. This patch doesn't handle 16-bit shrd/shld either. gcc/ChangeLog: PR target/55583 * config/i386/i386.md (*x86_64_shld_1): Rename to .. (x86_64_shld_1): .. this. (*x86_shld_1): Rename to .. (x86_shld_1): .. this. (*x86_64_shrd_1): Rename to .. (x86_64_shrd_1): .. this. (*x86_shrd_1): Rename to .. (x86_shrd_1): .. this. (*x86_64_shld_shrd_1_nozext): New pre_reload splitter. (*x86_shld_shrd_1_nozext): Ditto. (*x86_64_shrd_shld_1_nozext): Ditto. (*x86_shrd_shld_1_nozext): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr55583.c: New test.
This commit is contained in:
liuhongt
parent
af6d747df7
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5c5ef2f9ab
2 changed files with 173 additions and 4 deletions
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@ -12479,7 +12479,7 @@
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(set_attr "amdfam10_decode" "vector")
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(set_attr "bdver1_decode" "vector")])
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(define_insn "*x86_64_shld_1"
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(define_insn "x86_64_shld_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
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(ior:DI (ashift:DI (match_dup 0)
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(match_operand:QI 2 "const_0_to_63_operand"))
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@ -12500,6 +12500,42 @@
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(set_attr "amdfam10_decode" "vector")
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(set_attr "bdver1_decode" "vector")])
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(define_insn_and_split "*x86_64_shld_shrd_1_nozext"
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[(set (match_operand:DI 0 "nonimmediate_operand")
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(ior:DI (ashift:DI (match_operand:DI 4 "nonimmediate_operand")
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(match_operand:QI 2 "const_0_to_63_operand"))
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(lshiftrt:DI
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(match_operand:DI 1 "nonimmediate_operand")
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(match_operand:QI 3 "const_0_to_63_operand"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT
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&& INTVAL (operands[3]) == 64 - INTVAL (operands[2])
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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if (rtx_equal_p (operands[4], operands[0]))
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{
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operands[1] = force_reg (DImode, operands[1]);
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emit_insn (gen_x86_64_shld_1 (operands[0], operands[1], operands[2], operands[3]));
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}
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else if (rtx_equal_p (operands[1], operands[0]))
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{
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operands[4] = force_reg (DImode, operands[4]);
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emit_insn (gen_x86_64_shrd_1 (operands[0], operands[4], operands[3], operands[2]));
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}
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else
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{
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operands[1] = force_reg (DImode, operands[1]);
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rtx tmp = gen_reg_rtx (DImode);
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emit_move_insn (tmp, operands[4]);
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emit_insn (gen_x86_64_shld_1 (tmp, operands[1], operands[2], operands[3]));
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emit_move_insn (operands[0], tmp);
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}
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DONE;
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})
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(define_insn_and_split "*x86_64_shld_2"
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[(set (match_operand:DI 0 "nonimmediate_operand")
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(ior:DI (ashift:DI (match_dup 0)
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@ -12543,7 +12579,7 @@
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(set_attr "amdfam10_decode" "vector")
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(set_attr "bdver1_decode" "vector")])
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(define_insn "*x86_shld_1"
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(define_insn "x86_shld_1"
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[(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
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(ior:SI (ashift:SI (match_dup 0)
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(match_operand:QI 2 "const_0_to_31_operand"))
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@ -12564,6 +12600,41 @@
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(set_attr "amdfam10_decode" "vector")
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(set_attr "bdver1_decode" "vector")])
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(define_insn_and_split "*x86_shld_shrd_1_nozext"
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[(set (match_operand:SI 0 "nonimmediate_operand")
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(ior:SI (ashift:SI (match_operand:SI 4 "nonimmediate_operand")
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(match_operand:QI 2 "const_0_to_31_operand"))
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(lshiftrt:SI
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(match_operand:SI 1 "nonimmediate_operand")
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(match_operand:QI 3 "const_0_to_31_operand"))))
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(clobber (reg:CC FLAGS_REG))]
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"INTVAL (operands[3]) == 32 - INTVAL (operands[2])
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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if (rtx_equal_p (operands[4], operands[0]))
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{
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operands[1] = force_reg (SImode, operands[1]);
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emit_insn (gen_x86_shld_1 (operands[0], operands[1], operands[2], operands[3]));
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}
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else if (rtx_equal_p (operands[1], operands[0]))
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{
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operands[4] = force_reg (SImode, operands[4]);
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emit_insn (gen_x86_shrd_1 (operands[0], operands[4], operands[3], operands[2]));
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}
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else
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{
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operands[1] = force_reg (SImode, operands[1]);
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rtx tmp = gen_reg_rtx (SImode);
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emit_move_insn (tmp, operands[4]);
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emit_insn (gen_x86_shld_1 (tmp, operands[1], operands[2], operands[3]));
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emit_move_insn (operands[0], tmp);
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}
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DONE;
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})
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(define_insn_and_split "*x86_shld_2"
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[(set (match_operand:SI 0 "nonimmediate_operand")
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(ior:SI (ashift:SI (match_dup 0)
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@ -13442,7 +13513,7 @@
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(set_attr "amdfam10_decode" "vector")
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(set_attr "bdver1_decode" "vector")])
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(define_insn "*x86_64_shrd_1"
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(define_insn "x86_64_shrd_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
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(ior:DI (lshiftrt:DI (match_dup 0)
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(match_operand:QI 2 "const_0_to_63_operand"))
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@ -13463,6 +13534,42 @@
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(set_attr "amdfam10_decode" "vector")
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(set_attr "bdver1_decode" "vector")])
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(define_insn_and_split "*x86_64_shrd_shld_1_nozext"
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[(set (match_operand:DI 0 "nonimmediate_operand")
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(ior:DI (lshiftrt:DI (match_operand:DI 4 "nonimmediate_operand")
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(match_operand:QI 2 "const_0_to_63_operand"))
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(ashift:DI
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(match_operand:DI 1 "nonimmediate_operand")
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(match_operand:QI 3 "const_0_to_63_operand"))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT
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&& INTVAL (operands[3]) == 64 - INTVAL (operands[2])
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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if (rtx_equal_p (operands[4], operands[0]))
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{
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operands[1] = force_reg (DImode, operands[1]);
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emit_insn (gen_x86_64_shrd_1 (operands[0], operands[1], operands[2], operands[3]));
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}
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else if (rtx_equal_p (operands[1], operands[0]))
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{
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operands[4] = force_reg (DImode, operands[4]);
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emit_insn (gen_x86_64_shld_1 (operands[0], operands[4], operands[3], operands[2]));
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}
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else
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{
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operands[1] = force_reg (DImode, operands[1]);
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rtx tmp = gen_reg_rtx (DImode);
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emit_move_insn (tmp, operands[4]);
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emit_insn (gen_x86_64_shrd_1 (tmp, operands[1], operands[2], operands[3]));
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emit_move_insn (operands[0], tmp);
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}
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DONE;
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})
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(define_insn_and_split "*x86_64_shrd_2"
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[(set (match_operand:DI 0 "nonimmediate_operand")
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(ior:DI (lshiftrt:DI (match_dup 0)
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@ -13506,7 +13613,7 @@
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(set_attr "amdfam10_decode" "vector")
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(set_attr "bdver1_decode" "vector")])
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(define_insn "*x86_shrd_1"
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(define_insn "x86_shrd_1"
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[(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
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(ior:SI (lshiftrt:SI (match_dup 0)
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(match_operand:QI 2 "const_0_to_31_operand"))
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@ -13527,6 +13634,41 @@
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(set_attr "amdfam10_decode" "vector")
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(set_attr "bdver1_decode" "vector")])
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(define_insn_and_split "*x86_shrd_shld_1_nozext"
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[(set (match_operand:SI 0 "nonimmediate_operand")
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(ior:SI (lshiftrt:SI (match_operand:SI 4 "nonimmediate_operand")
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(match_operand:QI 2 "const_0_to_31_operand"))
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(ashift:SI
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(match_operand:SI 1 "nonimmediate_operand")
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(match_operand:QI 3 "const_0_to_31_operand"))))
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(clobber (reg:CC FLAGS_REG))]
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"INTVAL (operands[3]) == 32 - INTVAL (operands[2])
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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if (rtx_equal_p (operands[4], operands[0]))
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{
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operands[1] = force_reg (SImode, operands[1]);
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emit_insn (gen_x86_shrd_1 (operands[0], operands[1], operands[2], operands[3]));
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}
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else if (rtx_equal_p (operands[1], operands[0]))
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{
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operands[4] = force_reg (SImode, operands[4]);
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emit_insn (gen_x86_shld_1 (operands[0], operands[4], operands[3], operands[2]));
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}
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else
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{
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operands[1] = force_reg (SImode, operands[1]);
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rtx tmp = gen_reg_rtx (SImode);
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emit_move_insn (tmp, operands[4]);
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emit_insn (gen_x86_shrd_1 (tmp, operands[1], operands[2], operands[3]));
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emit_move_insn (operands[0], tmp);
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}
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DONE;
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})
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(define_insn_and_split "*x86_shrd_2"
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[(set (match_operand:SI 0 "nonimmediate_operand")
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(ior:SI (lshiftrt:SI (match_dup 0)
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27
gcc/testsuite/gcc.target/i386/pr55583.c
Normal file
27
gcc/testsuite/gcc.target/i386/pr55583.c
Normal file
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@ -0,0 +1,27 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -Wno-shift-count-overflow" } */
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/* { dg-final { scan-assembler-times {(?n)shrd[ql]?[\t ]*\$2} 4 { target { ! ia32 } } } } */
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/* { dg-final { scan-assembler-times {(?n)shrdl?[\t ]*\$2} 2 { target ia32 } } } */
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/* { dg-final { scan-assembler-times {(?n)shldl?[\t ]*\$2} 1 { target ia32 } } } */
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/* { dg-final { scan-assembler-times {(?n)shld[ql]?[\t ]*\$2} 2 { target { ! ia32 } } } } */
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typedef unsigned long u64;
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typedef unsigned int u32;
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typedef unsigned short u16;
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long a, b;
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int c, d;
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short e, f;
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const int n = 2;
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void test64r () { b = ((u64)b >> n) | (a << (64 - n)); }
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void test32r () { d = ((u32)d >> n) | (c << (32 - n)); }
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unsigned long ua, ub;
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unsigned int uc, ud;
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unsigned short ue, uf;
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void testu64l () { ub = (ub << n) | (ua >> (64 - n)); }
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void testu64r () { ub = (ub >> n) | (ua << (64 - n)); }
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void testu32l () { ud = (ud << n) | (uc >> (32 - n)); }
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void testu32r () { ud = (ud >> n) | (uc << (32 - n)); }
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