mips.h (reg_class): Remove HI_AND_GR_REGS...
gcc/ * config/mips/mips.h (reg_class): Remove HI_AND_GR_REGS, LO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS and ALL_COP_AND_GR_REGS. Add GR_AND_MD0_REGS, GR_AND_MD1_REGS, GR_AND_MD_REGS and GR_AND_ACC_REGS. (REG_CLASS_NAMES): Update accordingly. (REG_CLASS_CONTENTS): Likewise. Use the class name in the comments, rather than an unpredictable descriptive string. * config/mips/mips.c (mips_register_move_cost): Remove comment. (mips_register_move_cost): Check for specific COP*_REGS classes, instead of ALL_COP_AND_GR_REGS. (mips_ira_cover_classes): New function. (mips_secondary_reload_class): Remove MTLO and MTHI workarounds. (TARGET_IRA_COVER_CLASSES): Define. From-SVN: r141117
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
b17c40be65
commit
5c0a2e3ac5
3 changed files with 77 additions and 54 deletions
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@ -1,3 +1,20 @@
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2008-10-14 Richard Sandiford <rdsandiford@googlemail.com>
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* config/mips/mips.h (reg_class): Remove HI_AND_GR_REGS,
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LO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS,
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COP3_AND_GR_REGS, ALL_COP_REGS and ALL_COP_AND_GR_REGS.
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Add GR_AND_MD0_REGS, GR_AND_MD1_REGS, GR_AND_MD_REGS and
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GR_AND_ACC_REGS.
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(REG_CLASS_NAMES): Update accordingly.
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(REG_CLASS_CONTENTS): Likewise. Use the class name in the comments,
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rather than an unpredictable descriptive string.
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* config/mips/mips.c (mips_register_move_cost): Remove comment.
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(mips_register_move_cost): Check for specific COP*_REGS classes,
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instead of ALL_COP_AND_GR_REGS.
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(mips_ira_cover_classes): New function.
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(mips_secondary_reload_class): Remove MTLO and MTHI workarounds.
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(TARGET_IRA_COVER_CLASSES): Define.
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2008-10-14 Douglas Gregor <doug.gregor@gmail.com>
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PR c++/37553
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@ -9697,10 +9697,6 @@ mips_register_move_cost (enum machine_mode mode,
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{
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if (TARGET_MIPS16)
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{
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/* ??? We cannot move general registers into HI and LO because
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MIPS16 has no MTHI and MTLO instructions. Make the cost of
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moves in the opposite direction just as high, which stops the
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register allocators from using HI and LO for pseudos. */
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if (reg_class_subset_p (from, GENERAL_REGS)
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&& reg_class_subset_p (to, GENERAL_REGS))
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{
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@ -9717,7 +9713,9 @@ mips_register_move_cost (enum machine_mode mode,
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return 2;
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if (reg_class_subset_p (to, FP_REGS))
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return 4;
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if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS))
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if (reg_class_subset_p (to, COP0_REGS)
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|| reg_class_subset_p (to, COP2_REGS)
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|| reg_class_subset_p (to, COP3_REGS))
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return 5;
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if (reg_class_subset_p (to, ACC_REGS))
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return 6;
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@ -9729,7 +9727,9 @@ mips_register_move_cost (enum machine_mode mode,
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if (reg_class_subset_p (from, ST_REGS))
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/* LUI followed by MOVF. */
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return 4;
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if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS))
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if (reg_class_subset_p (from, COP0_REGS)
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|| reg_class_subset_p (from, COP2_REGS)
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|| reg_class_subset_p (from, COP3_REGS))
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return 5;
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if (reg_class_subset_p (from, ACC_REGS))
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return 6;
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@ -9747,6 +9747,25 @@ mips_register_move_cost (enum machine_mode mode,
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return 12;
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}
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/* Implement TARGET_IRA_COVER_CLASSES. */
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static const enum reg_class *
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mips_ira_cover_classes (void)
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{
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static const enum reg_class acc_classes[] = {
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GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
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ST_REGS, LIM_REG_CLASSES
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};
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static const enum reg_class no_acc_classes[] = {
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GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
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ST_REGS, LIM_REG_CLASSES
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};
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/* Don't allow the register allocators to use LO and HI in MIPS16 mode,
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which has no MTLO or MTHI instructions. */
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return TARGET_MIPS16 ? no_acc_classes : acc_classes;
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}
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/* Return the register class required for a secondary register when
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copying between one of the registers in RCLASS and value X, which
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has mode MODE. X is the source of the move if IN_P, otherwise it
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@ -9771,10 +9790,6 @@ mips_secondary_reload_class (enum reg_class rclass,
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if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
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return M16_REGS;
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/* We can't really copy to HI or LO at all in MIPS16 mode. */
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if (in_p ? reg_classes_intersect_p (rclass, ACC_REGS) : ACC_REG_P (regno))
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return M16_REGS;
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return NO_REGS;
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}
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@ -14203,6 +14218,9 @@ mips_order_regs_for_local_alloc (void)
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#undef TARGET_DWARF_REGISTER_SPAN
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#define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
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#undef TARGET_IRA_COVER_CLASSES
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#define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
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struct gcc_target targetm = TARGET_INITIALIZER;
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#include "gt-mips.h"
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@ -1796,18 +1796,14 @@ enum reg_class
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COP0_REGS, /* generic coprocessor classes */
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COP2_REGS,
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COP3_REGS,
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HI_AND_GR_REGS, /* union classes */
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LO_AND_GR_REGS,
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HI_AND_FP_REGS,
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COP0_AND_GR_REGS,
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COP2_AND_GR_REGS,
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COP3_AND_GR_REGS,
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ALL_COP_REGS,
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ALL_COP_AND_GR_REGS,
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ST_REGS, /* status registers (fp status) */
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DSP_ACC_REGS, /* DSP accumulator registers */
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ACC_REGS, /* Hi/Lo and DSP accumulator registers */
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FRAME_REGS, /* $arg and $frame */
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GR_AND_MD0_REGS, /* union classes */
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GR_AND_MD1_REGS,
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GR_AND_MD_REGS,
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GR_AND_ACC_REGS,
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ALL_REGS, /* all registers */
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LIM_REG_CLASSES /* max value + 1 */
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};
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@ -1838,18 +1834,14 @@ enum reg_class
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"COP0_REGS", \
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"COP2_REGS", \
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"COP3_REGS", \
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"HI_AND_GR_REGS", \
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"LO_AND_GR_REGS", \
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"HI_AND_FP_REGS", \
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"COP0_AND_GR_REGS", \
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"COP2_AND_GR_REGS", \
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"COP3_AND_GR_REGS", \
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"ALL_COP_REGS", \
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"ALL_COP_AND_GR_REGS", \
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"ST_REGS", \
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"DSP_ACC_REGS", \
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"ACC_REGS", \
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"FRAME_REGS", \
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"GR_AND_MD0_REGS", \
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"GR_AND_MD1_REGS", \
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"GR_AND_MD_REGS", \
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"GR_AND_ACC_REGS", \
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"ALL_REGS" \
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}
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@ -1866,34 +1858,30 @@ enum reg_class
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#define REG_CLASS_CONTENTS \
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{ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
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{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
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{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
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{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
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{ 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
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{ 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
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{ 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
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{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
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{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
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{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
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{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
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{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
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{ 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
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{ 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
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{ 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
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{ 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
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{ 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
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{ 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
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{ 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
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{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
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{ 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* frame registers */ \
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{ 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
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{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
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{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
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{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
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{ 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
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{ 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
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{ 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
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{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
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{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
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{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
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{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
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{ 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
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{ 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
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{ 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
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{ 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
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{ 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
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{ 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
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{ 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
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{ 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
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}
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