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i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV

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There is no need to set mode attribute to XImode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.

Remove ext_sse_reg_operand since it is no longer needed.

gcc/

	PR target/89229
	* config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
	for TYPE_SSEMOV.  Remove ext_sse_reg_operand and TARGET_AVX512VL
	check.
	* config/i386/predicates.md (ext_sse_reg_operand): Removed.

gcc/testsuite/

	PR target/89229
	* gcc.target/i386/pr89229-7a.c: New test.
	* gcc.target/i386/pr89229-7b.c: Likewise.
	* gcc.target/i386/pr89229-7c.c: Likewise.
This commit is contained in:
H.J. Lu 2020-03-16 03:48:55 -07:00
parent e41d4a0a56
commit 5a3c42b227
7 changed files with 47 additions and 28 deletions
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8
gcc/ChangeLog
View file

@ -1,3 +1,11 @@
2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
PR target/89229
* config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
check.
* config/i386/predicates.md (ext_sse_reg_operand): Removed.
2020-03-16 Jakub Jelinek <jakub@redhat.com>
PR debug/94167

25
gcc/config/i386/i386.md
View file

@ -2261,25 +2261,7 @@
gcc_unreachable ();
case TYPE_SSEMOV:
switch (get_attr_mode (insn))
{
case MODE_SI:
return "%vmovd\t{%1, %0|%0, %1}";
case MODE_TI:
return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_XI:
return "vmovdqa32\t{%g1, %g0|%g0, %g1}";
case MODE_V4SF:
return "%vmovaps\t{%1, %0|%0, %1}";
case MODE_SF:
gcc_assert (!TARGET_AVX);
return "movss\t{%1, %0|%0, %1}";
default:
gcc_unreachable ();
}
return ix86_output_ssemov (insn, operands);
case TYPE_MMX:
return "pxor\t%0, %0";
@ -2345,10 +2327,7 @@
(cond [(eq_attr "alternative" "2,3")
(const_string "DI")
(eq_attr "alternative" "8,9")
(cond [(ior (match_operand 0 "ext_sse_reg_operand")
(match_operand 1 "ext_sse_reg_operand"))
(const_string "XI")
(match_test "TARGET_AVX")
(cond [(match_test "TARGET_AVX")
(const_string "TI")
(ior (not (match_test "TARGET_SSE2"))
(match_test "optimize_function_for_size_p (cfun)"))

5
gcc/config/i386/predicates.md
View file

@ -61,11 +61,6 @@
(and (match_code "reg")
(match_test "SSE_REGNO_P (REGNO (op))")))
;; True if the operand is an AVX-512 new register.
(define_predicate "ext_sse_reg_operand"
(and (match_code "reg")
(match_test "EXT_REX_SSE_REGNO_P (REGNO (op))")))
;; Return true if op is a QImode register.
(define_predicate "any_QIreg_operand"
(and (match_code "reg")

7
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,10 @@
2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
PR target/89229
* gcc.target/i386/pr89229-7a.c: New test.
* gcc.target/i386/pr89229-7b.c: Likewise.
* gcc.target/i386/pr89229-7c.c: Likewise.
2020-03-16 Iain Buclaw <ibuclaw@gdcproject.org>
* gdc.dg/asm1.d: Add new test for ICE in asm parser.

17
gcc/testsuite/gcc.target/i386/pr89229-7a.c Normal file
View file

@ -0,0 +1,17 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -march=skylake-avx512" } */
extern int i;
int
foo1 (void)
{
register int xmm16 __asm ("xmm16") = i;
asm volatile ("" : "+v" (xmm16));
register int xmm17 __asm ("xmm17") = xmm16;
asm volatile ("" : "+v" (xmm17));
return xmm17;
}
/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */

6
gcc/testsuite/gcc.target/i386/pr89229-7b.c Normal file
View file

@ -0,0 +1,6 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */
#include "pr89229-7a.c"
/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*zmm1\[67]\[^\n\r]*zmm1\[67]" 1 } } */

7
gcc/testsuite/gcc.target/i386/pr89229-7c.c Normal file
View file

@ -0,0 +1,7 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */
#include "pr89229-7a.c"
/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */