i386: Use QImode for offsets in zero_extract/sign_extract in i386.md
As suggested by Uros, this patch changes the ZERO_EXTRACTs and SIGN_EXTRACTs in i386.md to consistently use QImode for bit offsets (i.e. third and fourth operands), matching the use of QImode for bit counts in shifts and rotates. There's no change in functionality, and the new patterns simply ensure that we continue to generate the same code (match revised patterns) as before. 2023-07-22 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * config/i386/i386.md (extv<mode>): Use QImode for offsets. (extzv<mode>): Likewise. (insv<mode>): Likewise. (*testqi_ext_3): Likewise. (*btr<mode>_2): Likewise. (define_split): Likewise. (*btsq_imm): Likewise. (*btrq_imm): Likewise. (*btcq_imm): Likewise. (define_peephole2 x3): Likewise. (*bt<mode>): Likewise (*bt<mode>_mask): New define_insn_and_split. (*jcc_bt<mode>): Use QImode for offsets. (*jcc_bt<mode>_1): Delete obsolete pattern. (*jcc_bt<mode>_mask): Use QImode offsets. (*jcc_bt<mode>_mask_1): Likewise. (define_split): Likewise. (*bt<mode>_setcqi): Likewise. (*bt<mode>_setncqi): Likewise. (*bt<mode>_setnc<mode>): Likewise. (*bt<mode>_setncqi_2): Likewise. (*bt<mode>_setc<mode>_mask): New define_insn_and_split. (bmi2_bzhi_<mode>3): Use QImode offsets. (*bmi2_bzhi_<mode>3): Likewise. (*bmi2_bzhi_<mode>3_1): Likewise. (*bmi2_bzhi_<mode>3_1_ccz): Likewise. (@tbm_bextri_<mode>): Likewise.
This commit is contained in:
Roger Sayle
parent
6ed43713e4
commit
59c38ddfe0
1 changed files with 103 additions and 109 deletions
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@ -3312,8 +3312,8 @@
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(define_expand "extv<mode>"
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[(set (match_operand:SWI24 0 "register_operand")
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(sign_extract:SWI24 (match_operand:SWI24 1 "register_operand")
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(match_operand:SI 2 "const_int_operand")
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(match_operand:SI 3 "const_int_operand")))]
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(match_operand:QI 2 "const_int_operand")
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(match_operand:QI 3 "const_int_operand")))]
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""
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{
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/* Handle extractions from %ah et al. */
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@ -3340,8 +3340,8 @@
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(define_expand "extzv<mode>"
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[(set (match_operand:SWI248 0 "register_operand")
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(zero_extract:SWI248 (match_operand:SWI248 1 "register_operand")
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(match_operand:SI 2 "const_int_operand")
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(match_operand:SI 3 "const_int_operand")))]
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(match_operand:QI 2 "const_int_operand")
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(match_operand:QI 3 "const_int_operand")))]
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""
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{
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if (ix86_expand_pextr (operands))
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@ -3428,8 +3428,8 @@
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(define_expand "insv<mode>"
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[(set (zero_extract:SWI248 (match_operand:SWI248 0 "register_operand")
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(match_operand:SI 1 "const_int_operand")
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(match_operand:SI 2 "const_int_operand"))
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(match_operand:QI 1 "const_int_operand")
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(match_operand:QI 2 "const_int_operand"))
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(match_operand:SWI248 3 "register_operand"))]
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""
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{
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@ -10788,8 +10788,8 @@
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(match_operator 1 "compare_operator"
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[(zero_extract:SWI248
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(match_operand 2 "int_nonimmediate_operand" "rm")
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(match_operand 3 "const_int_operand")
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(match_operand 4 "const_int_operand"))
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(match_operand:QI 3 "const_int_operand")
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(match_operand:QI 4 "const_int_operand"))
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(const_int 0)]))]
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"/* Ensure that resulting mask is zero or sign extended operand. */
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INTVAL (operands[4]) >= 0
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@ -15965,7 +15965,7 @@
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[(set (zero_extract:HI
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(match_operand:SWI12 0 "nonimmediate_operand")
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(const_int 1)
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(zero_extend:SI (match_operand:QI 1 "register_operand")))
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(match_operand:QI 1 "register_operand"))
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(const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_USE_BT && ix86_pre_reload_split ()"
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@ -15989,7 +15989,7 @@
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[(set (zero_extract:HI
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(match_operand:SWI12 0 "register_operand")
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(const_int 1)
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(zero_extend:SI (match_operand:QI 1 "register_operand")))
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(match_operand:QI 1 "register_operand"))
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(const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_USE_BT && ix86_pre_reload_split ()"
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@ -16016,7 +16016,7 @@
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(define_insn "*btsq_imm"
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[(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand"))
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(match_operand:QI 1 "const_0_to_63_operand"))
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(const_int 1))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
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@ -16029,7 +16029,7 @@
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(define_insn "*btrq_imm"
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[(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand"))
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(match_operand:QI 1 "const_0_to_63_operand"))
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(const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
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@ -16042,7 +16042,7 @@
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(define_insn "*btcq_imm"
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[(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand"))
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(match_operand:QI 1 "const_0_to_63_operand"))
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(not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
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@ -16059,7 +16059,7 @@
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(parallel [(set (zero_extract:DI
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(match_operand:DI 0 "nonimmediate_operand")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand"))
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(match_operand:QI 1 "const_0_to_63_operand"))
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(const_int 1))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_64BIT && !TARGET_USE_BT"
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@ -16083,7 +16083,7 @@
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(parallel [(set (zero_extract:DI
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(match_operand:DI 0 "nonimmediate_operand")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand"))
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(match_operand:QI 1 "const_0_to_63_operand"))
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(const_int 0))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_64BIT && !TARGET_USE_BT"
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@ -16107,7 +16107,7 @@
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(parallel [(set (zero_extract:DI
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(match_operand:DI 0 "nonimmediate_operand")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand"))
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(match_operand:QI 1 "const_0_to_63_operand"))
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(not:DI (zero_extract:DI
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(match_dup 0) (const_int 1) (match_dup 1))))
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(clobber (reg:CC FLAGS_REG))])]
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@ -16135,14 +16135,14 @@
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(zero_extract:SWI48
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(match_operand:SWI48 0 "nonimmediate_operand" "r,m")
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(const_int 1)
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(match_operand:SI 1 "nonmemory_operand" "r<S>,<S>"))
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(match_operand:QI 1 "nonmemory_operand" "q<S>,<S>"))
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(const_int 0)))]
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""
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{
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switch (get_attr_mode (insn))
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{
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case MODE_SI:
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return "bt{l}\t{%1, %k0|%k0, %1}";
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return "bt{l}\t{%k1, %k0|%k0, %k1}";
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case MODE_DI:
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return "bt{q}\t{%q1, %0|%0, %q1}";
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@ -16160,13 +16160,36 @@
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(const_string "SI")
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(const_string "<MODE>")))])
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(define_insn_and_split "*bt<SWI48:mode>_mask"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(zero_extract:SWI48
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(match_operand:SWI48 0 "nonimmediate_operand" "r,m")
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(const_int 1)
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(subreg:QI
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(and:SWI248
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(match_operand:SWI248 1 "register_operand")
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(match_operand 2 "const_int_operand")) 0))
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(const_int 0)))]
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"TARGET_USE_BT
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&& (INTVAL (operands[2]) & (GET_MODE_BITSIZE (<SWI48:MODE>mode)-1))
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== GET_MODE_BITSIZE (<SWI48:MODE>mode)-1
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(zero_extract:SWI48 (match_dup 0) (const_int 1) (match_dup 1))
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(const_int 0)))]
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"operands[1] = gen_lowpart (QImode, operands[1]);")
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(define_insn_and_split "*jcc_bt<mode>"
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[(set (pc)
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(if_then_else (match_operator 0 "bt_comparison_operator"
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[(zero_extract:SWI48
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(match_operand:SWI48 1 "nonimmediate_operand")
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(const_int 1)
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(match_operand:SI 2 "nonmemory_operand"))
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(match_operand:QI 2 "nonmemory_operand"))
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(const_int 0)])
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(label_ref (match_operand 3))
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(pc)))
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@ -16196,39 +16219,6 @@
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PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
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})
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(define_insn_and_split "*jcc_bt<mode>_1"
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[(set (pc)
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(if_then_else (match_operator 0 "bt_comparison_operator"
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[(zero_extract:SWI48
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(match_operand:SWI48 1 "register_operand")
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(const_int 1)
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(zero_extend:SI
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(match_operand:QI 2 "register_operand")))
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(const_int 0)])
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(label_ref (match_operand 3))
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(pc)))
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(clobber (reg:CC FLAGS_REG))]
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"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(zero_extract:SWI48
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(match_dup 1)
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(const_int 1)
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(match_dup 2))
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(const_int 0)))
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(set (pc)
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(if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
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(label_ref (match_dup 3))
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(pc)))]
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{
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operands[2] = lowpart_subreg (SImode, operands[2], QImode);
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operands[0] = shallow_copy_rtx (operands[0]);
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PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
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})
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;; Avoid useless masking of bit offset operand.
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(define_insn_and_split "*jcc_bt<mode>_mask"
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[(set (pc)
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@ -16236,8 +16226,8 @@
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[(zero_extract:SWI48
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(match_operand:SWI48 1 "register_operand")
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(const_int 1)
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(and:SI
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(match_operand:SI 2 "register_operand")
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(and:QI
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(match_operand:QI 2 "register_operand")
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(match_operand 3 "const_int_operand")))])
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(label_ref (match_operand 4))
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(pc)))
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@ -16264,23 +16254,23 @@
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PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
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})
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(define_insn_and_split "*jcc_bt<mode>_mask_1"
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;; Avoid useless masking of bit offset operand.
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(define_insn_and_split "*jcc_bt<SWI48:mode>_mask_1"
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[(set (pc)
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(if_then_else (match_operator 0 "bt_comparison_operator"
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(if_then_else (match_operator 0 "bt_comparison_operator"
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[(zero_extract:SWI48
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(match_operand:SWI48 1 "register_operand")
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(const_int 1)
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(zero_extend:SI
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(subreg:QI
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(and
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(match_operand 2 "int248_register_operand")
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(match_operand 3 "const_int_operand")) 0)))])
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(subreg:QI
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(and:SWI248
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(match_operand:SWI248 2 "register_operand")
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(match_operand 3 "const_int_operand")) 0))])
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(label_ref (match_operand 4))
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(pc)))
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(clobber (reg:CC FLAGS_REG))]
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"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
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== GET_MODE_BITSIZE (<MODE>mode)-1
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<SWI48:MODE>mode)-1))
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== GET_MODE_BITSIZE (<SWI48:MODE>mode)-1
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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@ -16296,10 +16286,9 @@
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(label_ref (match_dup 4))
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(pc)))]
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{
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operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
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operands[2] = gen_lowpart (SImode, operands[2]);
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operands[0] = shallow_copy_rtx (operands[0]);
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PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
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operands[2] = gen_lowpart (QImode, operands[2]);
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})
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;; Help combine recognize bt followed by cmov
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@ -16310,7 +16299,7 @@
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[(zero_extract:SWI48
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(match_operand:SWI48 1 "register_operand")
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(const_int 1)
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(zero_extend:SI (match_operand:QI 2 "register_operand")))
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(match_operand:QI 2 "register_operand"))
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(const_int 0)])
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(match_operand:SWI248 3 "nonimmediate_operand")
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(match_operand:SWI248 4 "nonimmediate_operand")))]
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@ -16328,7 +16317,6 @@
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{
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if (GET_CODE (operands[5]) == EQ)
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std::swap (operands[3], operands[4]);
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operands[2] = lowpart_subreg (SImode, operands[2], QImode);
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})
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;; Help combine recognize bt followed by setc
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@ -16337,7 +16325,7 @@
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(zero_extract:SWI48
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(match_operand:SWI48 1 "register_operand")
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(const_int 1)
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(zero_extend:SI (match_operand:QI 2 "register_operand"))))
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(match_operand:QI 2 "register_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_USE_BT && ix86_pre_reload_split ()"
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"#"
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@ -16347,8 +16335,7 @@
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(zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2))
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(const_int 0)))
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(set (match_dup 0)
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(eq:QI (reg:CCC FLAGS_REG) (const_int 0)))]
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"operands[2] = lowpart_subreg (SImode, operands[2], QImode);")
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(eq:QI (reg:CCC FLAGS_REG) (const_int 0)))])
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;; Help combine recognize bt followed by setnc
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(define_insn_and_split "*bt<mode>_setncqi"
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@ -16368,8 +16355,7 @@
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(zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2))
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(const_int 0)))
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(set (match_dup 0)
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(ne:QI (reg:CCC FLAGS_REG) (const_int 0)))]
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"operands[2] = lowpart_subreg (SImode, operands[2], QImode);")
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(ne:QI (reg:CCC FLAGS_REG) (const_int 0)))])
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(define_insn_and_split "*bt<mode>_setnc<mode>"
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[(set (match_operand:SWI48 0 "register_operand")
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@ -16389,10 +16375,7 @@
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(set (match_dup 3)
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(ne:QI (reg:CCC FLAGS_REG) (const_int 0)))
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(set (match_dup 0) (zero_extend:SWI48 (match_dup 3)))]
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{
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operands[2] = lowpart_subreg (SImode, operands[2], QImode);
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operands[3] = gen_reg_rtx (QImode);
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})
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"operands[3] = gen_reg_rtx (QImode);")
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;; Help combine recognize bt followed by setnc (PR target/110588)
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(define_insn_and_split "*bt<mode>_setncqi_2"
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@ -16401,7 +16384,7 @@
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(zero_extract:SWI48
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(match_operand:SWI48 1 "register_operand")
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(const_int 1)
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(zero_extend:SI (match_operand:QI 2 "register_operand")))
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(match_operand:QI 2 "register_operand"))
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(const_int 0)))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_USE_BT && ix86_pre_reload_split ()"
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@ -16412,8 +16395,36 @@
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(zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2))
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(const_int 0)))
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(set (match_dup 0)
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(ne:QI (reg:CCC FLAGS_REG) (const_int 0)))]
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"operands[2] = lowpart_subreg (SImode, operands[2], QImode);")
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(ne:QI (reg:CCC FLAGS_REG) (const_int 0)))])
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;; Help combine recognize bt followed by setc
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(define_insn_and_split "*bt<mode>_setc<mode>_mask"
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[(set (match_operand:SWI48 0 "register_operand")
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(zero_extract:SWI48
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(match_operand:SWI48 1 "register_operand")
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(const_int 1)
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(subreg:QI
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(and:SWI48
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||||
(match_operand:SWI48 2 "register_operand")
|
||||
(match_operand 3 "const_int_operand")) 0)))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_USE_BT
|
||||
&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
|
||||
== GET_MODE_BITSIZE (<MODE>mode)-1
|
||||
&& ix86_pre_reload_split ()"
|
||||
"#"
|
||||
"&& 1"
|
||||
[(set (reg:CCC FLAGS_REG)
|
||||
(compare:CCC
|
||||
(zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2))
|
||||
(const_int 0)))
|
||||
(set (match_dup 3)
|
||||
(ne:QI (reg:CCC FLAGS_REG) (const_int 0)))
|
||||
(set (match_dup 0) (zero_extend:SWI48 (match_dup 3)))]
|
||||
{
|
||||
operands[2] = gen_lowpart (QImode, operands[2]);
|
||||
operands[3] = gen_reg_rtx (QImode);
|
||||
})
|
||||
|
||||
;; Store-flag instructions.
|
||||
|
||||
|
|
@ -18708,46 +18719,29 @@
|
|||
[(parallel
|
||||
[(set (match_operand:SWI48 0 "register_operand")
|
||||
(if_then_else:SWI48
|
||||
(ne:QI (and:SWI48 (match_operand:SWI48 2 "register_operand")
|
||||
(const_int 255))
|
||||
(ne:QI (match_operand:QI 2 "register_operand")
|
||||
(const_int 0))
|
||||
(zero_extract:SWI48
|
||||
(match_operand:SWI48 1 "nonimmediate_operand")
|
||||
(umin:SWI48 (and:SWI48 (match_dup 2) (const_int 255))
|
||||
(match_dup 3))
|
||||
(umin:QI (match_dup 2) (match_dup 3))
|
||||
(const_int 0))
|
||||
(const_int 0)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_BMI2"
|
||||
"operands[3] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);")
|
||||
{
|
||||
operands[2] = gen_lowpart (QImode, operands[2]);
|
||||
operands[3] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
|
||||
})
|
||||
|
||||
(define_insn "*bmi2_bzhi_<mode>3"
|
||||
[(set (match_operand:SWI48 0 "register_operand" "=r")
|
||||
(if_then_else:SWI48
|
||||
(ne:QI (and:SWI48 (match_operand:SWI48 2 "register_operand" "r")
|
||||
(const_int 255))
|
||||
(ne:QI (match_operand:QI 2 "register_operand" "q")
|
||||
(const_int 0))
|
||||
(zero_extract:SWI48
|
||||
(match_operand:SWI48 1 "nonimmediate_operand" "rm")
|
||||
(umin:SWI48 (and:SWI48 (match_dup 2) (const_int 255))
|
||||
(match_operand:SWI48 3 "const_int_operand"))
|
||||
(const_int 0))
|
||||
(const_int 0)))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_BMI2 && INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT"
|
||||
"bzhi\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "bitmanip")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*bmi2_bzhi_<mode>3_1"
|
||||
[(set (match_operand:SWI48 0 "register_operand" "=r")
|
||||
(if_then_else:SWI48
|
||||
(ne:QI (match_operand:QI 2 "register_operand" "r") (const_int 0))
|
||||
(zero_extract:SWI48
|
||||
(match_operand:SWI48 1 "nonimmediate_operand" "rm")
|
||||
(umin:SWI48 (zero_extend:SWI48 (match_dup 2))
|
||||
(match_operand:SWI48 3 "const_int_operand"))
|
||||
(umin:QI (match_dup 2)
|
||||
(match_operand:QI 3 "const_int_operand"))
|
||||
(const_int 0))
|
||||
(const_int 0)))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
|
|
@ -18764,8 +18758,8 @@
|
|||
(ne:QI (match_operand:QI 2 "register_operand" "r") (const_int 0))
|
||||
(zero_extract:SWI48
|
||||
(match_operand:SWI48 1 "nonimmediate_operand" "rm")
|
||||
(umin:SWI48 (zero_extend:SWI48 (match_dup 2))
|
||||
(match_operand:SWI48 3 "const_int_operand"))
|
||||
(umin:QI (match_dup 2)
|
||||
(match_operand:QI 3 "const_int_operand"))
|
||||
(const_int 0))
|
||||
(const_int 0))
|
||||
(const_int 0)))
|
||||
|
|
@ -18864,8 +18858,8 @@
|
|||
[(set (match_operand:SWI48 0 "register_operand" "=r")
|
||||
(zero_extract:SWI48
|
||||
(match_operand:SWI48 1 "nonimmediate_operand" "rm")
|
||||
(match_operand 2 "const_0_to_255_operand")
|
||||
(match_operand 3 "const_0_to_255_operand")))
|
||||
(match_operand:QI 2 "const_0_to_255_operand")
|
||||
(match_operand:QI 3 "const_0_to_255_operand")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_TBM"
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue