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re PR target/71186 (PowerPC64: Autovectorised code hits ICE with -O3 -mpower9 -mlra)

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[gcc]
2016-05-31  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71186
	* config/rs6000/vsx.md (xxspltib_<mode>_nosplit): Add alternatives
	for loading up all 0's or all 1's.

[gcc/testsuite]
2016-05-31  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71186
	* gcc.target/powerpc/pr71186.c: New test.

Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md	(.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)	(revision 236935)
+++ gcc/config/rs6000/vsx.md	(.../gcc/config/rs6000)	(working copy)
@@ -776,8 +776,8 @@ (define_insn "xxspltib_v16qi"
   [(set_attr "type" "vecperm")])
 
 (define_insn "xxspltib_<mode>_nosplit"
-  [(set (match_operand:VSINT_842 0 "vsx_register_operand" "=wa")
-	(match_operand:VSINT_842 1 "xxspltib_constant_nosplit" "wE"))]
+  [(set (match_operand:VSINT_842 0 "vsx_register_operand" "=wa,wa")
+	(match_operand:VSINT_842 1 "xxspltib_constant_nosplit" "jwM,wE"))]
   "TARGET_P9_VECTOR"
 {
   rtx op1 = operands[1];

[gcc]
2016-05-31  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/vsx.md (vsx_splat_<mode>, V2DI/V2DF): Simplify
	alternatives, eliminating preferred register class.  Add support
	for the MTVSRDD instruction in ISA 3.0.
	(vsx_splat_v4si_internal): Use splat_input_operand instead of
	reg_or_indexed_operand.
	(vsx_splat_v4sf_internal): Likewise.

[gcc/testsuite]
2016-05-31  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-splat-4.c: New test.

From-SVN: r237006
This commit is contained in:
Michael Meissner 2016-06-01 20:09:35 +00:00 • committed by Michael Meissner
parent 4731c9f025
commit 58f2fb5ca1
5 changed files with 74 additions and 11 deletions
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15
gcc/ChangeLog
View file

@ -1,3 +1,18 @@
2016-05-31 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vsx.md (vsx_splat_<mode>, V2DI/V2DF): Simplify
alternatives, eliminating preferred register class. Add support
for the MTVSRDD instruction in ISA 3.0.
(vsx_splat_v4si_internal): Use splat_input_operand instead of
reg_or_indexed_operand.
(vsx_splat_v4sf_internal): Likewise.
2016-05-31 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/71186
* config/rs6000/vsx.md (xxspltib_<mode>_nosplit): Add alternatives
for loading up all 0's or all 1's.
2016-06-01 Thomas Preud'homme <thomas.preudhomme@arm.com>
* doc/sourcebuild.texi (arm_acq_rel): Document new effective target.

19
gcc/config/rs6000/vsx.md
View file

@ -776,8 +776,8 @@
[(set_attr "type" "vecperm")])
(define_insn "xxspltib_<mode>_nosplit"
[(set (match_operand:VSINT_842 0 "vsx_register_operand" "=wa")
(match_operand:VSINT_842 1 "xxspltib_constant_nosplit" "wE"))]
[(set (match_operand:VSINT_842 0 "vsx_register_operand" "=wa,wa")
(match_operand:VSINT_842 1 "xxspltib_constant_nosplit" "jwM,wE"))]
"TARGET_P9_VECTOR"
{
rtx op1 = operands[1];
@ -2384,18 +2384,15 @@
;; V2DF/V2DI splat
(define_insn "vsx_splat_<mode>"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?<VSa>,?<VSa>,?<VSa>")
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>,<VSa>,we")
(vec_duplicate:VSX_D
(match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,f,Z,<VSa>,<VSa>,Z")))]
(match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,Z,b")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
xxpermdi %x0,%x1,%x1,0
xxpermdi %x0,%x1,%x1,0
lxvdsx %x0,%y1
xxpermdi %x0,%x1,%x1,0
xxpermdi %x0,%x1,%x1,0
lxvdsx %x0,%y1"
[(set_attr "type" "vecperm,vecperm,vecload,vecperm,vecperm,vecload")])
mtvsrdd %x0,%1,%1"
[(set_attr "type" "vecperm,vecload,mftgpr")])
;; V4SI splat (ISA 3.0)
;; When SI's are allowed in VSX registers, add XXSPLTW support
@ -2414,7 +2411,7 @@
(define_insn "*vsx_splat_v4si_internal"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
(vec_duplicate:V4SI
(match_operand:SI 1 "reg_or_indexed_operand" "r,Z")))]
(match_operand:SI 1 "splat_input_operand" "r,Z")))]
"TARGET_P9_VECTOR"
"@
mtvsrws %x0,%1
@ -2425,7 +2422,7 @@
(define_insn_and_split "*vsx_splat_v4sf_internal"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,wa")
(vec_duplicate:V4SF
(match_operand:SF 1 "reg_or_indexed_operand" "Z,wy,r")))]
(match_operand:SF 1 "splat_input_operand" "Z,wy,r")))]
"TARGET_P9_VECTOR"
"@
lxvwsx %x0,%y1

9
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,12 @@
2016-05-31 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-splat-4.c: New test.
2016-05-31 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/71186
* gcc.target/powerpc/pr71186.c: New test.
2016-06-01 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR fortran/52393

10
gcc/testsuite/gcc.target/powerpc/p9-splat-4.c Normal file
View file

@ -0,0 +1,10 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -O2" } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
#include <altivec.h>
vector long long foo (long long a) { return (vector long long) { a, a }; }
/* { dg-final { scan-assembler "mtvsrdd" } } */

32
gcc/testsuite/gcc.target/powerpc/pr71186.c Normal file
View file

@ -0,0 +1,32 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -O2" } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
static unsigned short x[(16384/sizeof(unsigned short))] __attribute__ ((aligned (16)));
static unsigned short y[(16384/sizeof(unsigned short))] __attribute__ ((aligned (16)));
static unsigned short a;
void obfuscate(void *a, ...);
static void __attribute__((noinline)) do_one(void)
{
unsigned long i;
obfuscate(x, y, &a);
for (i = 0; i < (16384/sizeof(unsigned short)); i++)
y[i] = a * x[i];
obfuscate(x, y, &a);
}
int main(void)
{
unsigned long i;
for (i = 0; i < 1000000; i++)
do_one();
return 0;
}