[PATCH, PR target/94954] Fix wrong codegen for vec_pack_to_short_fp32() builtin
Hi, Fix codegen for builtin vec_pack_to_short_fp32. This includes adding a define_insn for xvcvsphp, and adding a new define_expand for convert_4f32_8f16. 2020-06-24 Will Schmidt <will_schmidt@vnet.ibm.com> PR target/94954 gcc * config/rs6000/altivec.h (vec_pack_to_short_fp32): Update. * config/rs6000/altivec.md (UNSPEC_CONVERT_4F32_8F16): New unspec. (convert_4f32_8f16): New define_expand * config/rs6000/rs6000-builtin.def (convert_4f32_8f16): New builtin define and overload. * config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_CONVERT_4F32_8F16): New overloaded builtin entry. * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPHP): New unspec. (vsx_xvcvsphp): New define_insn. gcc/testsuite * gcc.target/powerpc/builtins-1-p9-runnable.c: Update.
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Will Schmidt
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ef6506e236
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58b475a223
6 changed files with 83 additions and 10 deletions
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@ -433,7 +433,7 @@
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#define vec_first_match_or_eos_index __builtin_vec_first_match_or_eos_index
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#define vec_first_mismatch_index __builtin_vec_first_mismatch_index
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#define vec_first_mismatch_or_eos_index __builtin_vec_first_mismatch_or_eos_index
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#define vec_pack_to_short_fp32 __builtin_vec_convert_4f32_8i16
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#define vec_pack_to_short_fp32 __builtin_vec_convert_4f32_8f16
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#define vec_parity_lsbb __builtin_vec_vparity_lsbb
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#define vec_vctz __builtin_vec_vctz
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#define vec_cnttz __builtin_vec_vctz
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@ -80,6 +80,7 @@
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UNSPEC_VUPKHPX
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UNSPEC_VUPKLPX
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UNSPEC_CONVERT_4F32_8I16
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UNSPEC_CONVERT_4F32_8F16
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UNSPEC_DST
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UNSPEC_DSTT
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UNSPEC_DSTST
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@ -3217,6 +3218,39 @@
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DONE;
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})
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;; Convert two vector F32 to packed vector F16.
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;; This builtin packs 32-bit floating-point values into a packed
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;; 16-bit floating point values (stored in 16bit integer type).
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;; (vector unsigned short r = vec_pack_to_short_fp32 (a, b);
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;; The expected codegen for this builtin is
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;; xvcvsphp t, a
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;; xvcvsphp u, b
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;; if (little endian)
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;; vpkuwum r, t, u
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;; else
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;; vpkuwum r, u, t
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(define_expand "convert_4f32_8f16"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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(unspec:V8HI [(match_operand:V4SF 1 "register_operand" "v")
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(match_operand:V4SF 2 "register_operand" "v")]
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UNSPEC_CONVERT_4F32_8F16))]
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"TARGET_P9_VECTOR"
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{
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rtx rtx_tmp_hi = gen_reg_rtx (V4SImode);
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rtx rtx_tmp_lo = gen_reg_rtx (V4SImode);
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emit_insn (gen_vsx_xvcvsphp (rtx_tmp_hi, operands[1]));
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emit_insn (gen_vsx_xvcvsphp (rtx_tmp_lo, operands[2]));
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if (!BYTES_BIG_ENDIAN)
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emit_insn (gen_altivec_vpkuwum (operands[0], rtx_tmp_hi, rtx_tmp_lo));
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else
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emit_insn (gen_altivec_vpkuwum (operands[0], rtx_tmp_lo, rtx_tmp_hi));
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DONE;
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})
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;; Generate
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;; xxlxor/vxor SCRATCH0,SCRATCH0,SCRATCH0
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;; vsubu?m SCRATCH2,SCRATCH1,%1
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@ -2289,6 +2289,7 @@ BU_P8V_OVERLOAD_3 (VPERMXOR, "vpermxor")
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BU_P9V_AV_2 (VSLV, "vslv", CONST, vslv)
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BU_P9V_AV_2 (VSRV, "vsrv", CONST, vsrv)
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BU_P9V_AV_2 (CONVERT_4F32_8I16, "convert_4f32_8i16", CONST, convert_4f32_8i16)
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BU_P9V_AV_2 (CONVERT_4F32_8F16, "convert_4f32_8f16", CONST, convert_4f32_8f16)
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BU_P9V_AV_2 (VFIRSTMATCHINDEX_V16QI, "first_match_index_v16qi",
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CONST, first_match_index_v16qi)
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@ -2319,6 +2320,7 @@ BU_P9V_AV_2 (VFIRSTMISMATCHOREOSINDEX_V4SI, "first_mismatch_or_eos_index_v4si",
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BU_P9V_OVERLOAD_2 (VSLV, "vslv")
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BU_P9V_OVERLOAD_2 (VSRV, "vsrv")
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BU_P9V_OVERLOAD_2 (CONVERT_4F32_8I16, "convert_4f32_8i16")
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BU_P9V_OVERLOAD_2 (CONVERT_4F32_8F16, "convert_4f32_8f16")
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/* 2 argument vector functions added in ISA 3.0 (power9). */
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BU_P9V_AV_2 (VADUB, "vadub", CONST, vaduv16qi3)
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@ -1985,6 +1985,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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{ P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
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{ P9V_BUILTIN_VEC_CONVERT_4F32_8F16, P9V_BUILTIN_CONVERT_4F32_8F16,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
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{ P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI,
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RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
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@ -299,6 +299,7 @@
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UNSPEC_VSX_XVCVBF16SP
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UNSPEC_VSX_XVCVSPBF16
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UNSPEC_VSX_XVCVSPSXDS
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UNSPEC_VSX_XVCVSPHP
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UNSPEC_VSX_VSLO
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UNSPEC_VSX_EXTRACT
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UNSPEC_VSX_SXEXPDP
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@ -2187,6 +2188,15 @@
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"xvcvhpsp %x0,%x1"
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[(set_attr "type" "vecfloat")])
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;; Generate xvcvsphp
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(define_insn "vsx_xvcvsphp"
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[(set (match_operand:V4SI 0 "register_operand" "=wa")
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(unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
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UNSPEC_VSX_XVCVSPHP))]
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"TARGET_P9_VECTOR"
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"xvcvsphp %x0,%x1"
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[(set_attr "type" "vecfloat")])
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;; xscvdpsp used for splat'ing a scalar to V4SF, knowing that the internal SF
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;; format of scalars is actually DF.
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(define_insn "vsx_xscvdpsp_scalar"
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@ -1,25 +1,50 @@
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/* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-do run { target { powerpc*-*-linux* && p9vector_hw } } } */
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/* { dg-require-effective-target p9vector_hw } */
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/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
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#include <altivec.h>
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#include <stdio.h>
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void abort (void);
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int main() {
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int i;
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vector float vfa, vfb;
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vector unsigned short vur, vuexpt;
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vector unsigned short vresult, vexpected;
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vfa = (vector float){3.4, 5.0, 20.0, 50.9 };
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vfb = (vector float){10.0, 40.0, 70.0, 100.0 };
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vuexpt = (vector unsigned short){ 3, 5, 20, 50,
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10, 40, 70, 100};
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vfa = (vector float){0.4, 1.6, 20.0, 99.9 };
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vfb = (vector float){10.0, -2.0, 70.0, 999.0 };
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vur = vec_pack_to_short_fp32 (vfa, vfb);
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/* Expected results. */
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vexpected = (vector unsigned short) { 0x3666, 0x3e66, 0x4d00, 0x563e,
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0x4900, 0xc000, 0x5460, 0x63ce};
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/*
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vresult = vec_pack_to_short_fp32 (vfa, vfb);
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This built-in converts a pair of vector floats into a single vector of
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packed half-precision (F16) values. The result type is a vector of
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signed shorts.
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The expected codegen for this builtin is
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xvcvsphp t, vfa
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xvcvsphp u, vfb
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if (little endian)
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vpkuwum vresult, t, u
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else
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vpkuwum vresult, u, t
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*/
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vresult = vec_pack_to_short_fp32 (vfa, vfb);
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#ifdef DEBUG
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for(i = 0; i< 4; i++) { printf("i=[%d] %f \n",i,vfa[i]); }
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for(i = 0; i< 4; i++) { printf("i=[%d] %f \n",i+4,vfb[i]); }
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for(i = 0; i< 8; i++) { printf("i=[%d] %d \n",i,vresult[i]); }
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#endif
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for(i = 0; i< 8; i++) {
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if (vur[i] != vuexpt[i])
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if (vresult[i] != vexpected[i]) {
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printf("i=[%d] 0x%x != 0x%x \n",i,vresult[i],vexpected[i]);
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abort();
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}
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}
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}
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