i386: Add insert and extract patterns for 4-byte vectors [PR100637]
The patch introduces insert and extract patterns for 4-byte vectors. It effectively only emits PINSR and PEXTR instructions when available, otherwise falls back to generic code that emulates these instructions via inserts, extracts, logic operations and shifts in integer registers. Please note that generic fallback produces better code than the current approach of constructing new vector in memory (due to store forwarding stall) so also enable QImode 8-byte vector inserts only with TARGET_SSE4_1. 2021-06-03 Uroš Bizjak <ubizjak@gmail.com> gcc/ PR target/100637 * config/i386/i386-expand.c (ix86_expand_vector_set): Handle V2HI and V4QI modes. (ix86_expand_vector_extract): Ditto. * config/i386/mmx.md (*pinsrw): New insn pattern. (*pinsrb): Ditto. (*pextrw): Ditto. (*pextrw_zext): Ditto. (*pextrb): Ditto. (*pextrb_zext): Ditto. (vec_setv2hi): New expander. (vec_extractv2hihi): Ditto. (vec_setv4qi): Ditto. (vec_extractv4qiqi): Ditto. (vec_setv8qi): Enable only for TARGET_SSE4_1. (vec_extractv8qiqi): Ditto. gcc/testsuite/ PR target/100637 * gcc.target/i386/vperm-v2hi.c: New test. * gcc.target/i386/vperm-v4qi.c: Ditto.
This commit is contained in:
Uros Bizjak
parent
52e130652a
commit
5883e56756
4 changed files with 268 additions and 2 deletions
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@ -14968,6 +14968,7 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
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return;
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case E_V8HImode:
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case E_V2HImode:
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use_vec_merge = TARGET_SSE2;
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break;
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case E_V4HImode:
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@ -14975,6 +14976,7 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
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break;
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case E_V16QImode:
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case E_V4QImode:
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use_vec_merge = TARGET_SSE4_1;
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break;
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@ -15274,6 +15276,7 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
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break;
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case E_V8HImode:
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case E_V2HImode:
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use_vec_extr = TARGET_SSE2;
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break;
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case E_V4HImode:
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@ -15294,6 +15297,9 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
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return;
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}
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break;
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case E_V4QImode:
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use_vec_extr = TARGET_SSE4_1;
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break;
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case E_V8SFmode:
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if (TARGET_AVX)
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@ -3092,7 +3092,7 @@
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[(match_operand:V8QI 0 "register_operand")
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(match_operand:QI 1 "register_operand")
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(match_operand 2 "const_int_operand")]
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"TARGET_MMX || TARGET_MMX_WITH_SSE"
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"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
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{
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ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
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INTVAL (operands[2]));
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@ -3103,7 +3103,7 @@
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[(match_operand:QI 0 "register_operand")
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(match_operand:V8QI 1 "register_operand")
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(match_operand 2 "const_int_operand")]
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"TARGET_MMX || TARGET_MMX_WITH_SSE"
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"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
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{
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ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
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operands[1], INTVAL (operands[2]));
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@ -3120,6 +3120,178 @@
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DONE;
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})
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(define_insn "*pinsrw"
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[(set (match_operand:V2HI 0 "register_operand" "=x,YW")
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(vec_merge:V2HI
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(vec_duplicate:V2HI
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(match_operand:HI 2 "nonimmediate_operand" "rm,rm"))
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(match_operand:V2HI 1 "register_operand" "0,YW")
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(match_operand:SI 3 "const_int_operand")))]
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"TARGET_SSE2
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&& ((unsigned) exact_log2 (INTVAL (operands[3]))
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< GET_MODE_NUNITS (V2HImode))"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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switch (which_alternative)
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{
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case 1:
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if (MEM_P (operands[2]))
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return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
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else
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return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
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case 0:
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if (MEM_P (operands[2]))
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return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
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else
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return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "length_immediate" "1")
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(set_attr "mode" "TI")])
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(define_insn "*pinsrb"
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[(set (match_operand:V4QI 0 "register_operand" "=x,YW")
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(vec_merge:V4QI
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(vec_duplicate:V4QI
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(match_operand:QI 2 "nonimmediate_operand" "rm,rm"))
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(match_operand:V4QI 1 "register_operand" "0,YW")
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(match_operand:SI 3 "const_int_operand")))]
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"TARGET_SSE4_1
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&& ((unsigned) exact_log2 (INTVAL (operands[3]))
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< GET_MODE_NUNITS (V4QImode))"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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switch (which_alternative)
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{
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case 1:
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if (MEM_P (operands[2]))
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return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
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else
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return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
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case 0:
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if (MEM_P (operands[2]))
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return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
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else
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return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix_data16" "1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "TI")])
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(define_insn "*pextrw"
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[(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,m")
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(vec_select:HI
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(match_operand:V2HI 1 "register_operand" "YW,YW")
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(parallel [(match_operand:SI 2 "const_0_to_1_operand" "n,n")])))]
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"TARGET_SSE2"
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"@
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%vpextrw\t{%2, %1, %k0|%k0, %1, %2}
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%vpextrw\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "*,sse4")
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(set_attr "type" "sselog1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*pextrw_zext"
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[(set (match_operand:SWI48 0 "register_operand" "=r")
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(zero_extend:SWI48
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(vec_select:HI
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(match_operand:V2HI 1 "register_operand" "YW")
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(parallel [(match_operand:SI 2 "const_0_to_1_operand" "n")]))))]
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"TARGET_SSE2"
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"%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
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[(set_attr "type" "sselog1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*pextrb"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,m")
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(vec_select:QI
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(match_operand:V4QI 1 "register_operand" "YW,YW")
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(parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")])))]
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"TARGET_SSE4_1"
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"@
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%vpextrb\t{%2, %1, %k0|%k0, %1, %2}
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%vpextrb\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sselog1")
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(set_attr "prefix_data16" "1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*pextrb_zext"
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[(set (match_operand:SWI248 0 "register_operand" "=r")
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(zero_extend:SWI248
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(vec_select:QI
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(match_operand:V4QI 1 "register_operand" "YW")
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(parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
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"TARGET_SSE4_1"
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"%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
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[(set_attr "type" "sselog1")
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(set_attr "prefix_data16" "1")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_expand "vec_setv2hi"
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[(match_operand:V2HI 0 "register_operand")
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(match_operand:HI 1 "register_operand")
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(match_operand 2 "const_int_operand")]
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"TARGET_SSE2"
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{
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ix86_expand_vector_set (false, operands[0], operands[1],
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INTVAL (operands[2]));
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DONE;
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})
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(define_expand "vec_extractv2hihi"
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[(match_operand:HI 0 "register_operand")
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(match_operand:V2HI 1 "register_operand")
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(match_operand 2 "const_int_operand")]
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"TARGET_SSE2"
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{
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ix86_expand_vector_extract (false, operands[0],
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operands[1], INTVAL (operands[2]));
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DONE;
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})
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(define_expand "vec_setv4qi"
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[(match_operand:V4QI 0 "register_operand")
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(match_operand:QI 1 "register_operand")
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(match_operand 2 "const_int_operand")]
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"TARGET_SSE4_1"
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{
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ix86_expand_vector_set (false, operands[0], operands[1],
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INTVAL (operands[2]));
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DONE;
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})
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(define_expand "vec_extractv4qiqi"
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[(match_operand:QI 0 "register_operand")
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(match_operand:V4QI 1 "register_operand")
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(match_operand 2 "const_int_operand")]
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"TARGET_SSE4_1"
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{
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ix86_expand_vector_extract (false, operands[0],
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operands[1], INTVAL (operands[2]));
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DONE;
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})
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Miscellaneous
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41
gcc/testsuite/gcc.target/i386/vperm-v2hi.c
Normal file
41
gcc/testsuite/gcc.target/i386/vperm-v2hi.c
Normal file
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@ -0,0 +1,41 @@
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/* { dg-do run } */
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/* { dg-options "-O -msse2" } */
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/* { dg-require-effective-target sse2 } */
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#include "isa-check.h"
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#include "sse-os-support.h"
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typedef short S;
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typedef short V __attribute__((vector_size(4)));
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typedef short IV __attribute__((vector_size(4)));
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typedef union { S s[2]; V v; } U;
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static U i[2], b, c;
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extern int memcmp (const void *, const void *, __SIZE_TYPE__);
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#define assert(T) ((T) || (__builtin_trap (), 0))
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#define TEST(E0, E1) \
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b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1}); \
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c.s[0] = i[0].s[E0]; \
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c.s[1] = i[0].s[E1]; \
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__asm__("" : : : "memory"); \
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assert (memcmp (&b, &c, sizeof(c)) == 0);
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#include "vperm-2-2.inc"
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int main()
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{
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check_isa ();
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if (!sse_os_support ())
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exit (0);
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i[0].s[0] = 0;
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i[0].s[1] = 1;
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i[0].s[2] = 2;
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i[0].s[3] = 3;
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check();
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return 0;
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}
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47
gcc/testsuite/gcc.target/i386/vperm-v4qi.c
Normal file
47
gcc/testsuite/gcc.target/i386/vperm-v4qi.c
Normal file
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@ -0,0 +1,47 @@
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/* { dg-do run } */
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/* { dg-options "-O -msse2" } */
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/* { dg-require-effective-target sse2 } */
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#include "isa-check.h"
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#include "sse-os-support.h"
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typedef char S;
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typedef char V __attribute__((vector_size(4)));
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typedef char IV __attribute__((vector_size(4)));
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typedef union { S s[4]; V v; } U;
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static U i[2], b, c;
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extern int memcmp (const void *, const void *, __SIZE_TYPE__);
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#define assert(T) ((T) || (__builtin_trap (), 0))
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#define TEST(E0, E1, E2, E3) \
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b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \
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c.s[0] = i[0].s[E0]; \
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c.s[1] = i[0].s[E1]; \
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c.s[2] = i[0].s[E2]; \
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c.s[3] = i[0].s[E3]; \
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__asm__("" : : : "memory"); \
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assert (memcmp (&b, &c, sizeof(c)) == 0);
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#include "vperm-4-2.inc"
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int main()
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{
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check_isa ();
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if (!sse_os_support ())
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exit (0);
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i[0].s[0] = 0;
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i[0].s[1] = 1;
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i[0].s[2] = 2;
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i[0].s[3] = 3;
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i[0].s[4] = 4;
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i[0].s[5] = 5;
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i[0].s[6] = 6;
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i[0].s[7] = 7;
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check();
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return 0;
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}
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