RISC-V: Remove redundant codes of VLS patterns[NFC]
Consider those VLS patterns are the same VLA patterns. Now extend VI -> V_VLSI and VF -> V_VLSF. Then remove the redundant codes of VLS patterns. gcc/ChangeLog: * config/riscv/autovec-vls.md (<optab><mode>3): Deleted. (copysign<mode>3): Ditto. (xorsign<mode>3): Ditto. (<optab><mode>2): Ditto. * config/riscv/autovec.md: Extend VLS modes.
This commit is contained in:
Juzhe-Zhong
Lehua Ding
parent
55b22a6f63
commit
5761dce5d7
2 changed files with 22 additions and 160 deletions
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@ -194,141 +194,3 @@
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}
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[(set_attr "type" "vector")]
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] Binary operations
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - vadd.vv/vsub.vv/...
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;; - vadd.vi/vsub.vi/...
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;; -------------------------------------------------------------------------
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(define_insn_and_split "<optab><mode>3"
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[(set (match_operand:VLSI 0 "register_operand")
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(any_int_binop_no_shift:VLSI
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(match_operand:VLSI 1 "<binop_rhs1_predicate>")
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(match_operand:VLSI 2 "<binop_rhs2_predicate>")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
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riscv_vector::BINARY_OP, operands);
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DONE;
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}
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[(set_attr "type" "vector")]
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)
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;; -------------------------------------------------------------------------
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;; ---- [FP] Binary operations
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - vfadd.vv/vfsub.vv/vfmul.vv/vfdiv.vv
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;; - vfadd.vf/vfsub.vf/vfmul.vf/vfdiv.vf
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;; -------------------------------------------------------------------------
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(define_insn_and_split "<optab><mode>3"
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[(set (match_operand:VLSF 0 "register_operand")
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(any_float_binop:VLSF
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(match_operand:VLSF 1 "<binop_rhs1_predicate>")
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(match_operand:VLSF 2 "<binop_rhs2_predicate>")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
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riscv_vector::BINARY_OP_FRM_DYN, operands);
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DONE;
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}
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[(set_attr "type" "vector")]
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)
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - vfmin.vv/vfmax.vv
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;; - vfmin.vf/vfmax.vf
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;; - fmax/fmaxf in math.h
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;; -------------------------------------------------------------------------
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(define_insn_and_split "<optab><mode>3"
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[(set (match_operand:VLSF 0 "register_operand")
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(any_float_binop_nofrm:VLSF
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(match_operand:VLSF 1 "<binop_rhs1_predicate>")
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(match_operand:VLSF 2 "<binop_rhs2_predicate>")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
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riscv_vector::BINARY_OP, operands);
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DONE;
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}
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[(set_attr "type" "vector")]
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)
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - vfsgnj.vv
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;; - vfsgnj.vf
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;; -------------------------------------------------------------------------
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(define_insn_and_split "copysign<mode>3"
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[(set (match_operand:VLSF 0 "register_operand")
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(unspec:VLSF
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[(match_operand:VLSF 1 "register_operand")
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(match_operand:VLSF 2 "register_operand")] UNSPEC_VCOPYSIGN))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VCOPYSIGN, <MODE>mode),
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riscv_vector::BINARY_OP, operands);
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DONE;
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}
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[(set_attr "type" "vector")]
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)
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - vfsgnjx.vv
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;; - vfsgnjx.vf
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;; -------------------------------------------------------------------------
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(define_insn_and_split "xorsign<mode>3"
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[(set (match_operand:VLSF 0 "register_operand")
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(unspec:VLSF
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[(match_operand:VLSF 1 "register_operand")
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(match_operand:VLSF 2 "register_operand")] UNSPEC_VXORSIGN))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, <MODE>mode),
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riscv_vector::BINARY_OP, operands);
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DONE;
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}
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)
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;; -------------------------------------------------------------------------------
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;; ---- [INT] Unary operations
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;; -------------------------------------------------------------------------------
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;; Includes:
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;; - vneg.v/vnot.v
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;; -------------------------------------------------------------------------------
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(define_insn_and_split "<optab><mode>2"
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[(set (match_operand:VLSI 0 "register_operand")
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(any_int_unop:VLSI
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(match_operand:VLSI 1 "register_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred (<CODE>, <MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
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DONE;
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}
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[(set_attr "type" "vector")]
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)
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@ -420,10 +420,10 @@
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;; -------------------------------------------------------------------------
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(define_insn_and_split "<optab><mode>3"
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[(set (match_operand:VI 0 "register_operand")
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(any_int_binop_no_shift:VI
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(match_operand:VI 1 "<binop_rhs1_predicate>")
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(match_operand:VI 2 "<binop_rhs2_predicate>")))]
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[(set (match_operand:V_VLSI 0 "register_operand")
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(any_int_binop_no_shift:V_VLSI
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(match_operand:V_VLSI 1 "<binop_rhs1_predicate>")
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(match_operand:V_VLSI 2 "<binop_rhs2_predicate>")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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@ -985,9 +985,9 @@
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;; - vneg.v/vnot.v
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;; -------------------------------------------------------------------------------
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(define_insn_and_split "<optab><mode>2"
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[(set (match_operand:VI 0 "register_operand")
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(any_int_unop:VI
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(match_operand:VI 1 "register_operand")))]
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[(set (match_operand:V_VLSI 0 "register_operand")
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(any_int_unop:V_VLSI
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(match_operand:V_VLSI 1 "register_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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@ -1516,10 +1516,10 @@
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;; - vfadd.vf/vfsub.vf/...
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;; -------------------------------------------------------------------------
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(define_insn_and_split "<optab><mode>3"
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[(set (match_operand:VF 0 "register_operand")
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(any_float_binop:VF
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(match_operand:VF 1 "register_operand")
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(match_operand:VF 2 "register_operand")))]
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[(set (match_operand:V_VLSF 0 "register_operand")
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(any_float_binop:V_VLSF
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(match_operand:V_VLSF 1 "register_operand")
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(match_operand:V_VLSF 2 "register_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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@ -1537,10 +1537,10 @@
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;; - vfmin.vf/vfmax.vf
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;; -------------------------------------------------------------------------
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(define_insn_and_split "<optab><mode>3"
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[(set (match_operand:VF 0 "register_operand")
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(any_float_binop_nofrm:VF
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(match_operand:VF 1 "register_operand")
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(match_operand:VF 2 "register_operand")))]
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[(set (match_operand:V_VLSF 0 "register_operand")
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(any_float_binop_nofrm:V_VLSF
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(match_operand:V_VLSF 1 "register_operand")
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(match_operand:V_VLSF 2 "register_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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@ -1563,10 +1563,10 @@
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;; Leave the pattern like this as to still allow combine to match
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;; a negated copysign (see vector.md) before adding the UNSPEC_VPREDICATE later.
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(define_insn_and_split "copysign<mode>3"
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[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
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(unspec:VF
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[(match_operand:VF 1 "register_operand" " vr, vr, vr, vr")
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(match_operand:VF 2 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))]
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[(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
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(unspec:V_VLSF
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[(match_operand:V_VLSF 1 "register_operand" " vr, vr, vr, vr")
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(match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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@ -1585,9 +1585,9 @@
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;; - vfsgnjx.vf
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;; -------------------------------------------------------------------------------
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(define_expand "xorsign<mode>3"
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[(match_operand:VF 0 "register_operand")
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(match_operand:VF 1 "register_operand")
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(match_operand:VF 2 "register_operand")]
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[(match_operand:V_VLSF 0 "register_operand")
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(match_operand:V_VLSF 1 "register_operand")
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(match_operand:V_VLSF 2 "register_operand")]
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"TARGET_VECTOR"
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{
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riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, <MODE>mode),
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