re PR rtl-optimization/87361 (gcc.target/sparc/20161111-1.c FAILs)
PR rtl-optimization/87361 * rtlanal.c (nonzero_bits1): Revert accidental change. From-SVN: r264420
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2 changed files with 8 additions and 3 deletions
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2018-09-19 Eric Botcazou <ebotcazou@adacore.com>
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PR rtl-optimization/87361
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* rtlanal.c (nonzero_bits1): Revert accidental change.
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2018-09-19 Richard Biener <rguenther@suse.de>
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PR tree-optimization/87349
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@ -4758,17 +4758,17 @@ nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
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nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
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known_x, known_mode, known_ret);
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/* On many CISC machines, accessing an object in a wider mode
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/* On many CISC machines, accessing an object in a wider mode
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causes the high-order bits to become undefined. So they are
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not known to be zero. */
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rtx_code extend_op;
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if ((!WORD_REGISTER_OPERATIONS
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/* If this is a typical RISC machine, we only have to worry
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about the way loads are extended. */
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|| !MEM_P (SUBREG_REG (x))
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|| ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND
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? val_signbit_known_set_p (inner_mode, nonzero)
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: extend_op != ZERO_EXTEND))
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: extend_op != ZERO_EXTEND)
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|| (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x))))
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&& xmode_width > inner_width)
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nonzero
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|= (GET_MODE_MASK (GET_MODE (x)) & ~GET_MODE_MASK (inner_mode));
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