RISC-V: Add support for XCVsimd extension in CV32E40P
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVbitmanip. * config/riscv/constraints.md: Likewise. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/predicates.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'. * doc/extend.texi: Add XCVbitmanip builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-simd-abs-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-abs-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxconj-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-march-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-packhi-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-packlo-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c: New test. * lib/target-supports.exp: Add proc for XCVsimd extension.
This commit is contained in:
Mary Bennett
Kito Cheng
parent
3fc39658df
commit
5739d5fb54
173 changed files with 7662 additions and 0 deletions
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@ -356,6 +356,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
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{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xcvsimd", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
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@ -1600,6 +1601,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
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{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
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{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
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{"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
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{"xcvsimd", &gcc_options::x_riscv_xcv_subext, MASK_XCVSIMD},
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{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
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{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
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@ -55,6 +55,11 @@
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(and (match_code "const_int")
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(match_test "ival == 2")))
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(define_constraint "c03"
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"Constant value 3"
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(and (match_code "const_int")
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(match_test "ival == 3")))
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(define_constraint "c04"
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"Constant value 4"
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(and (match_code "const_int")
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@ -262,3 +267,28 @@
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(and (match_code "const_int")
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(and (match_test "IN_RANGE (ival, 0, 1073741823)")
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(match_test "exact_log2 (ival + 1) != -1"))))
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(define_constraint "CV_simd_si6"
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"A 6-bit signed immediate for SIMD."
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, -32, 31)")))
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(define_constraint "CV_simd_un6"
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"A 6-bit unsigned immediate for SIMD."
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, 0, 63)")))
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(define_constraint "CV_simd_i01"
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"Shifting immediate for SIMD shufflei1."
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, 64, 127)")))
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(define_constraint "CV_simd_i02"
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"Shifting immediate for SIMD shufflei2."
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, -128, -65)")))
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(define_constraint "CV_simd_i03"
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"Shifting immediate for SIMD shufflei3."
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, -64, -1)")))
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@ -44,3 +44,159 @@ RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_
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// XCVELW
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RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw),
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// XCVSIMD
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//ALU Operations
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RISCV_BUILTIN (cv_simd_add_h_si, "cv_simd_add_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd),
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RISCV_BUILTIN (cv_simd_add_b_si, "cv_simd_add_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
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RISCV_BUILTIN (cv_simd_add_sc_h_si, "cv_simd_add_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
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RISCV_BUILTIN (cv_simd_add_sc_b_si, "cv_simd_add_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
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RISCV_BUILTIN (cv_simd_sub_h_si, "cv_simd_sub_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd),
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RISCV_BUILTIN (cv_simd_sub_b_si, "cv_simd_sub_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
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RISCV_BUILTIN (cv_simd_sub_sc_h_si, "cv_simd_sub_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
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RISCV_BUILTIN (cv_simd_sub_sc_b_si, "cv_simd_sub_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
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RISCV_BUILTIN (cv_simd_avg_h_si, "cv_simd_avg_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
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RISCV_BUILTIN (cv_simd_avg_b_si, "cv_simd_avg_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
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RISCV_BUILTIN (cv_simd_avg_sc_h_si, "cv_simd_avg_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
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RISCV_BUILTIN (cv_simd_avg_sc_b_si, "cv_simd_avg_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
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RISCV_BUILTIN (cv_simd_avgu_h_si, "cv_simd_avgu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
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RISCV_BUILTIN (cv_simd_avgu_b_si, "cv_simd_avgu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
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RISCV_BUILTIN (cv_simd_avgu_sc_h_si, "cv_simd_avgu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd),
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RISCV_BUILTIN (cv_simd_avgu_sc_b_si, "cv_simd_avgu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
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RISCV_BUILTIN (cv_simd_min_h_si, "cv_simd_min_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
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RISCV_BUILTIN (cv_simd_min_b_si, "cv_simd_min_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
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RISCV_BUILTIN (cv_simd_min_sc_h_si, "cv_simd_min_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
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RISCV_BUILTIN (cv_simd_min_sc_b_si, "cv_simd_min_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
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RISCV_BUILTIN (cv_simd_minu_h_si, "cv_simd_minu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
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RISCV_BUILTIN (cv_simd_minu_b_si, "cv_simd_minu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_minu_sc_h_si, "cv_simd_minu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_minu_sc_b_si, "cv_simd_minu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_max_h_si, "cv_simd_max_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_max_b_si, "cv_simd_max_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_max_sc_h_si, "cv_simd_max_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_max_sc_b_si, "cv_simd_max_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_maxu_h_si, "cv_simd_maxu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_maxu_b_si, "cv_simd_maxu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_maxu_sc_h_si, "cv_simd_maxu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_maxu_sc_b_si, "cv_simd_maxu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_srl_h_si, "cv_simd_srl_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_srl_b_si, "cv_simd_srl_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_srl_sc_h_si, "cv_simd_srl_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_srl_sc_b_si, "cv_simd_srl_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sra_h_si, "cv_simd_sra_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sra_b_si, "cv_simd_sra_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sra_sc_h_si, "cv_simd_sra_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sra_sc_b_si, "cv_simd_sra_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sll_h_si, "cv_simd_sll_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sll_b_si, "cv_simd_sll_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sll_sc_h_si, "cv_simd_sll_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sll_sc_b_si, "cv_simd_sll_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_or_h_si, "cv_simd_or_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_or_b_si, "cv_simd_or_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_or_sc_h_si, "cv_simd_or_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_or_sc_b_si, "cv_simd_or_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_xor_h_si, "cv_simd_xor_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_xor_b_si, "cv_simd_xor_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_xor_sc_h_si, "cv_simd_xor_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_xor_sc_b_si, "cv_simd_xor_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_and_h_si, "cv_simd_and_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_and_b_si, "cv_simd_and_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_and_sc_h_si, "cv_simd_and_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_and_sc_b_si, "cv_simd_and_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_abs_h_si, "cv_simd_abs_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_abs_b_si, "cv_simd_abs_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_neg_h_si, "cv_simd_neg_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_neg_b_si, "cv_simd_neg_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd),
|
||||
//BIT MANIPULATION
|
||||
RISCV_BUILTIN (cv_simd_extract_h_si, "cv_simd_extract_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_extract_b_si, "cv_simd_extract_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_extractu_h_si, "cv_simd_extractu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_extractu_b_si, "cv_simd_extractu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_insert_h_si, "cv_simd_insert_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_insert_b_si, "cv_simd_insert_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_QI, cvsimd),
|
||||
//DOT PRODUCT
|
||||
RISCV_BUILTIN (cv_simd_dotup_h_si, "cv_simd_dotup_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotup_b_si, "cv_simd_dotup_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotup_sc_h_si, "cv_simd_dotup_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotup_sc_b_si, "cv_simd_dotup_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotusp_h_si, "cv_simd_dotusp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotusp_b_si, "cv_simd_dotusp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotusp_sc_h_si, "cv_simd_dotusp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotusp_sc_b_si, "cv_simd_dotusp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotsp_h_si, "cv_simd_dotsp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotsp_b_si, "cv_simd_dotsp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotsp_sc_h_si, "cv_simd_dotsp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_dotsp_sc_b_si, "cv_simd_dotsp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotup_h_si, "cv_simd_sdotup_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotup_b_si, "cv_simd_sdotup_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotup_sc_h_si, "cv_simd_sdotup_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotup_sc_b_si, "cv_simd_sdotup_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotusp_h_si, "cv_simd_sdotusp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotusp_b_si, "cv_simd_sdotusp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotusp_sc_h_si, "cv_simd_sdotusp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotusp_sc_b_si, "cv_simd_sdotusp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotsp_h_si, "cv_simd_sdotsp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotsp_b_si, "cv_simd_sdotsp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotsp_sc_h_si, "cv_simd_sdotsp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_sdotsp_sc_b_si, "cv_simd_sdotsp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI_USI, cvsimd),
|
||||
//SHUFFLE AND PACK
|
||||
RISCV_BUILTIN (cv_simd_shuffle_h_si, "cv_simd_shuffle_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_shuffle_sci_h_si, "cv_simd_shuffle_sci_h",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_shuffle_b_si, "cv_simd_shuffle_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_shuffle_sci_b_si, "cv_simd_shuffle_sci_b",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_shuffle2_h_si, "cv_simd_shuffle2_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_shuffle2_b_si, "cv_simd_shuffle2_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_packhi_h_si, "cv_simd_packhi_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_packlo_h_si, "cv_simd_packlo_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_packhi_b_si, "cv_simd_packhi_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_packlo_b_si, "cv_simd_packlo_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
//RISCV_BUILTIN (cv_simd_pack_si, "cv_simd_pack", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
//RISCV_BUILTIN (cv_simd_pack_h_si, "cv_simd_pack_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
//RISCV_BUILTIN (cv_simd_packhi_b_si, "cv_simd_packhi_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
//RISCV_BUILTIN (cv_simd_packlo_b_si, "cv_simd_packlo_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd),
|
||||
//COMPARISON OPERATIONS
|
||||
RISCV_BUILTIN (cv_simd_cmpeq_h_si, "cv_simd_cmpeq_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpeq_b_si, "cv_simd_cmpeq_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpeq_sc_h_si, "cv_simd_cmpeq_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpeq_sc_b_si, "cv_simd_cmpeq_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpne_h_si, "cv_simd_cmpne_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpne_b_si, "cv_simd_cmpne_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpne_sc_h_si, "cv_simd_cmpne_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpne_sc_b_si, "cv_simd_cmpne_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgt_h_si, "cv_simd_cmpgt_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgt_b_si, "cv_simd_cmpgt_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgt_sc_h_si, "cv_simd_cmpgt_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgt_sc_b_si, "cv_simd_cmpgt_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpge_h_si, "cv_simd_cmpge_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpge_b_si, "cv_simd_cmpge_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpge_sc_h_si, "cv_simd_cmpge_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpge_sc_b_si, "cv_simd_cmpge_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmplt_h_si, "cv_simd_cmplt_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmplt_b_si, "cv_simd_cmplt_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmplt_sc_h_si, "cv_simd_cmplt_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmplt_sc_b_si, "cv_simd_cmplt_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmple_h_si, "cv_simd_cmple_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmple_b_si, "cv_simd_cmple_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmple_sc_h_si, "cv_simd_cmple_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmple_sc_b_si, "cv_simd_cmple_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgtu_h_si, "cv_simd_cmpgtu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgtu_b_si, "cv_simd_cmpgtu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgtu_sc_h_si, "cv_simd_cmpgtu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgtu_sc_b_si, "cv_simd_cmpgtu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgeu_h_si, "cv_simd_cmpgeu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgeu_b_si, "cv_simd_cmpgeu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgeu_sc_h_si, "cv_simd_cmpgeu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpgeu_sc_b_si, "cv_simd_cmpgeu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpltu_h_si, "cv_simd_cmpltu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpltu_b_si, "cv_simd_cmpltu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpltu_sc_h_si, "cv_simd_cmpltu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpltu_sc_b_si, "cv_simd_cmpltu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpleu_h_si, "cv_simd_cmpleu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpleu_b_si, "cv_simd_cmpleu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpleu_sc_h_si, "cv_simd_cmpleu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cmpleu_sc_b_si, "cv_simd_cmpleu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd),
|
||||
//COMPLEX NUMBER
|
||||
RISCV_BUILTIN (cv_simd_cplxmul_r_si, "cv_simd_cplxmul_r", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cplxmul_i_si, "cv_simd_cplxmul_i", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_cplxconj_si, "cv_simd_cplxconj", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd),
|
||||
RISCV_BUILTIN (cv_simd_subrotmj_si, "cv_simd_subrotmj", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd),
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -425,6 +425,26 @@
|
|||
(ior (match_operand 0 "register_operand")
|
||||
(match_code "const_int")))
|
||||
|
||||
(define_predicate "const_int6s_operand"
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (INTVAL (op), -32, 31)")))
|
||||
|
||||
(define_predicate "int6s_operand"
|
||||
(ior (match_operand 0 "const_int6s_operand")
|
||||
(match_operand 0 "register_operand")))
|
||||
|
||||
(define_predicate "const_int2_operand"
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (INTVAL (op), 0, 3)")))
|
||||
|
||||
(define_predicate "const_int6_operand"
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (INTVAL (op), 0, 63)")))
|
||||
|
||||
(define_predicate "int6_operand"
|
||||
(ior (match_operand 0 "const_int6_operand")
|
||||
(match_operand 0 "register_operand")))
|
||||
|
||||
;; Predicates for the V extension.
|
||||
(define_special_predicate "vector_length_operand"
|
||||
(ior (match_operand 0 "pmode_register_operand")
|
||||
|
|
|
|||
|
|
@ -135,6 +135,7 @@ AVAIL (hint_pause, (!0))
|
|||
AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
|
||||
AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
|
||||
AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
|
||||
AVAIL (cvsimd, TARGET_XCVSIMD && !TARGET_64BIT)
|
||||
|
||||
/* Construct a riscv_builtin_description from the given arguments.
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,9 @@ DEF_RISCV_FTYPE (1, (USI, UHI))
|
|||
DEF_RISCV_FTYPE (1, (SI, QI))
|
||||
DEF_RISCV_FTYPE (1, (SI, HI))
|
||||
DEF_RISCV_FTYPE (2, (USI, UQI, UQI))
|
||||
DEF_RISCV_FTYPE (2, (USI, USI, UHI))
|
||||
DEF_RISCV_FTYPE (2, (USI, USI, QI))
|
||||
DEF_RISCV_FTYPE (2, (USI, USI, HI))
|
||||
DEF_RISCV_FTYPE (2, (USI, UHI, UHI))
|
||||
DEF_RISCV_FTYPE (2, (USI, USI, USI))
|
||||
DEF_RISCV_FTYPE (2, (USI, USI, UQI))
|
||||
|
|
@ -50,6 +53,11 @@ DEF_RISCV_FTYPE (2, (UDI, UDI, UDI))
|
|||
DEF_RISCV_FTYPE (2, (SI, USI, USI))
|
||||
DEF_RISCV_FTYPE (2, (SI, SI, SI))
|
||||
DEF_RISCV_FTYPE (3, (USI, USI, USI, UQI))
|
||||
DEF_RISCV_FTYPE (3, (USI, USI, USI, QI))
|
||||
DEF_RISCV_FTYPE (3, (USI, USI, UQI, USI))
|
||||
DEF_RISCV_FTYPE (3, (USI, USI, QI, USI))
|
||||
DEF_RISCV_FTYPE (3, (USI, USI, UHI, USI))
|
||||
DEF_RISCV_FTYPE (3, (USI, USI, HI, USI))
|
||||
DEF_RISCV_FTYPE (3, (USI, USI, USI, USI))
|
||||
DEF_RISCV_FTYPE (3, (SI, SI, SI, UQI))
|
||||
DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
|
||||
|
|
|
|||
|
|
@ -5851,6 +5851,14 @@ riscv_print_operand (FILE *file, rtx op, int letter)
|
|||
output_addr_const (file, newop);
|
||||
break;
|
||||
}
|
||||
case 'Y':
|
||||
{
|
||||
unsigned int imm = (UINTVAL (op) & 63);
|
||||
gcc_assert (imm <= 63);
|
||||
rtx newop = GEN_INT (imm);
|
||||
output_addr_const (file, newop);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
switch (code)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -425,6 +425,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
|
|||
|
||||
Mask(XCVELW) Var(riscv_xcv_subext)
|
||||
|
||||
Mask(XCVSIMD) Var(riscv_xcv_subext)
|
||||
|
||||
TargetVariable
|
||||
int riscv_xthead_subext
|
||||
|
||||
|
|
|
|||
|
|
@ -24288,6 +24288,8 @@ All of these functions are declared in the include file @file{riscv_vector.h}.
|
|||
|
||||
@node CORE-V Built-in Functions
|
||||
@subsection CORE-V Built-in Functions
|
||||
For more information on all CORE-V built-ins, please see
|
||||
@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md}
|
||||
|
||||
These built-in functions are available for the CORE-V MAC machine
|
||||
architecture. For more information on CORE-V built-ins, please see
|
||||
|
|
@ -24467,6 +24469,890 @@ architecture. For more information on CORE-V ELW builtins, please see
|
|||
Generated assembler @code{cv.elw}
|
||||
@end deftypefn
|
||||
|
||||
These built-in functions are available for the CORE-V SIMD machine
|
||||
architecture. For more information on CORE-V SIMD built-ins, please see
|
||||
@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-pulp-816-bit-simd-builtins-xcvsimd}
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.add.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.add.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.add.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.add.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.add.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.add.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.sub.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sub.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.sub.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.sub.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.sub.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.sub.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.avg.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.avg.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.avg.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.avg.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.avg.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.avg.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.avgu.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.avgu.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_h (uint32_t, uint16_t)
|
||||
Generated assembler @code{cv.avgu.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.avgu.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_b (uint32_t, uint8_t)
|
||||
Generated assembler @code{cv.avgu.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.avgu.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.min.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.min.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.min.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.min.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.min.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.min.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.minu.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.minu.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_h (uint32_t, uint16_t)
|
||||
Generated assembler @code{cv.minu.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.minu.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_b (uint32_t, uint8_t)
|
||||
Generated assembler @code{cv.minu.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.minu.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.max.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.max.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.max.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.max.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.max.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.max.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.maxu.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.maxu.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_h (uint32_t, uint16_t)
|
||||
Generated assembler @code{cv.maxu.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.maxu.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_b (uint32_t, uint8_t)
|
||||
Generated assembler @code{cv.maxu.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.maxu.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.srl.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.srl.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.srl.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.srl.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.srl.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.srl.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sra.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sra.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.sra.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.sra.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.sra.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.sra.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sll.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sll.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.sll.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.sll.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.sll.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.sll.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.or.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.or.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.or.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.or.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.or.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.or.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.xor.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.xor.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.xor.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.xor.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.xor.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.xor.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.and.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.and.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.and.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.and.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.and.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.and.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_abs_h (uint32_t)
|
||||
Generated assembler @code{cv.abs.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_abs_b (uint32_t)
|
||||
Generated assembler @code{cv.abs.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.dotup.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.dotup.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_h (uint32_t, uint16_t)
|
||||
Generated assembler @code{cv.dotup.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.dotup.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_b (uint32_t, uint8_t)
|
||||
Generated assembler @code{cv.dotup.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.dotup.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.dotusp.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.dotusp.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.dotusp.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.dotusp.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.dotusp.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.dotusp.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.dotsp.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.dotsp.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.dotsp.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.dotsp.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.dotsp.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.dotsp.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_h (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotup.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_b (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotup.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_h (uint32_t, uint16_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotup.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_h (uint32_t, uint6_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotup.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_b (uint32_t, uint8_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotup.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_b (uint32_t, uint6_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotup.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_h (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotusp.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_b (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotusp.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_h (uint32_t, int16_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotusp.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_h (uint32_t, int6_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotusp.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_b (uint32_t, int8_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotusp.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_b (uint32_t, int6_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotusp.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_h (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotsp.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_b (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotsp.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_h (uint32_t, int16_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotsp.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_h (uint32_t, int6_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotsp.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_b (uint32_t, int8_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotsp.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_b (uint32_t, int6_t, uint32_t)
|
||||
Generated assembler @code{cv.sdotsp.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extract_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.extract.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extract_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.extract.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extractu_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.extractu.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extractu_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.extractu.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_insert_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.insert.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_insert_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.insert.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.shuffle.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.shuffle.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_sci_h (uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.shuffle.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei0_sci_b (uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.shufflei0.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei1_sci_b (uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.shufflei1.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei2_sci_b (uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.shufflei2.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei3_sci_b (uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.shufflei3.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle2_h (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.shuffle2.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle2_b (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.shuffle2.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packlo_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.pack}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packhi_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.pack.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packhi_b (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.packhi.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packlo_b (uint32_t, uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.packlo.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpeq.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpeq.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.cmpeq.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmpeq.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.cmpeq.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmpeq.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpne.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpne.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.cmpne.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmpne.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.cmpne.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmpne.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpgt.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpgt.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.cmpgt.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmpgt.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.cmpgt.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmpgt.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpge.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpge.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.cmpge.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmpge.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.cmpge.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmpge.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmplt.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmplt.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.cmplt.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmplt.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.cmplt.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmplt.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmple.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmple.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_h (uint32_t, int16_t)
|
||||
Generated assembler @code{cv.cmple.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_h (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmple.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_b (uint32_t, int8_t)
|
||||
Generated assembler @code{cv.cmple.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_b (uint32_t, int6_t)
|
||||
Generated assembler @code{cv.cmple.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpgtu.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpgtu.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_h (uint32_t, uint16_t)
|
||||
Generated assembler @code{cv.cmpgtu.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.cmpgtu.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_b (uint32_t, uint8_t)
|
||||
Generated assembler @code{cv.cmpgtu.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.cmpgtu.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpgeu.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpgeu.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_h (uint32_t, uint16_t)
|
||||
Generated assembler @code{cv.cmpgeu.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.cmpgeu.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_b (uint32_t, uint8_t)
|
||||
Generated assembler @code{cv.cmpgeu.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.cmpgeu.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpltu.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpltu.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_h (uint32_t, uint16_t)
|
||||
Generated assembler @code{cv.cmpltu.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.cmpltu.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_b (uint32_t, uint8_t)
|
||||
Generated assembler @code{cv.cmpltu.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.cmpltu.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_h (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpleu.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_b (uint32_t, uint32_t)
|
||||
Generated assembler @code{cv.cmpleu.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_h (uint32_t, uint16_t)
|
||||
Generated assembler @code{cv.cmpleu.sc.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_h (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.cmpleu.sci.h}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_b (uint32_t, uint8_t)
|
||||
Generated assembler @code{cv.cmpleu.sc.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_b (uint32_t, uint6_t)
|
||||
Generated assembler @code{cv.cmpleu.sci.b}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.cplxmul.r}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.cplxmul.i}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.cplxmul.r.div2}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.cplxmul.i.div2}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.cplxmul.r.div4}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.cplxmul.i.div4}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.cplxmul.r.div8}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.cplxmul.i.div8}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxconj (uint32_t)
|
||||
Generated assembler @code{cv.cplxconj}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.subrotmj}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.subrotmj.div2}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.subrotmj.div4}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.subrotmj.div8}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.add.div2}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.add.div4}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.add.div8}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.sub.div2}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.sub.div4}
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t)
|
||||
Generated assembler @code{cv.sub.div8}
|
||||
@end deftypefn
|
||||
|
||||
@node RX Built-in Functions
|
||||
@subsection RX Built-in Functions
|
||||
GCC supports some of the RX instructions which cannot be expressed in
|
||||
|
|
|
|||
|
|
@ -2525,6 +2525,9 @@ Test system has support for the CORE-V ALU extension.
|
|||
@item cv_elw
|
||||
Test system has support for the CORE-V ELW extension.
|
||||
|
||||
@item cv_simd
|
||||
Test system has support for the CORE-V SIMD extension.
|
||||
|
||||
@end table
|
||||
|
||||
@subsubsection Other hardware attributes
|
||||
|
|
|
|||
11
gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_abs_b(a);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.abs\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_abs_h(a);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.abs\\.h" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.add\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_h(a, b, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.add\\.div2" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_h(a, b, 2);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.add\\.div4" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_h(a, b, 3);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.add\\.div8" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_h(a, b, 0);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.add\\.h" 1 } } */
|
||||
30
gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c
Normal file
30
gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.b" 3 } } */
|
||||
30
gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c
Normal file
30
gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_add_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.and\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.and\\.h" 1 } } */
|
||||
30
gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c
Normal file
30
gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.b" 3 } } */
|
||||
30
gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c
Normal file
30
gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_and_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.avg\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.avg\\.h" 1 } } */
|
||||
30
gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c
Normal file
30
gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.b" 3 } } */
|
||||
30
gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c
Normal file
30
gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avg_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avgu_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.avgu\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avgu_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.avgu\\.h" 1 } } */
|
||||
24
gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c
Normal file
24
gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avgu_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avgu_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avgu_sc_b(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.b" 2 } } */
|
||||
24
gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c
Normal file
24
gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avgu_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avgu_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_avgu_sc_h(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.h" 2 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.b" 3 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpge\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpge\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.b" 3 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpge_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgeu_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgeu_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.b" 2 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.h" 2 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.b" 3 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgtu_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgtu_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.b" 2 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.h" 2 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmple\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmple\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.b" 3 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmple_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpleu_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpleu_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpleu_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.b" 2 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpleu_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.h" 2 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmplt\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmplt\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.b" 3 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmplt_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpltu_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpltu_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpltu_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.b" 2 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpltu_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.h" 2 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpne\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpne\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.b" 3 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cmpne_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cplxconj(a);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cplxconj" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b, int c)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 0);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i" 1 } } */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b, int c)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div2" 1 } } */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b, int c)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 2);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div4" 1 } } */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b, int c)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 3);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div8" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b, int c)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 0);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r" 1 } } */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b, int c)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div2" 1 } } */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b, int c)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 2);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div4" 1 } } */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b, int c)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 3);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div8" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotsp\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotsp\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.b" 3 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotsp_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.h" 3 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotup_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotup\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotup_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotup\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotup_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotup_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotup_sc_b(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.b" 2 } } */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotup_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotup_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotup_sc_h(a, 63);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.h" 2 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_b(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotusp\\.b" 1 } } */
|
||||
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c
Normal file
11
gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_h(a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotusp\\.h" 1 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_sc_b(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_sc_b(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_sc_b(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_sc_b(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.b" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.b" 3 } } */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_sc_h(a, b);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_sc_h(a, -32);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_sc_h(a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo4 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_dotusp_sc_h(a, 31);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.h" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.h" 3 } } */
|
||||
23
gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c
Normal file
23
gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extract_b (a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extract_b (a, 3);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extract_b (a, 255);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.extract\\.b" 3 } } */
|
||||
23
gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c
Normal file
23
gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extract_h (a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extract_h (a, 1);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extract_h (a, 255);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.extract\\.h" 3 } } */
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extractu_b (a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extractu_b (a, 3);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extractu_b (a, 255);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.extractu\\.b" 3 } } */
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extractu_h (a, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extractu_h (a, 1);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_extractu_h (a, 255);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.extractu\\.h" 3 } } */
|
||||
23
gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c
Normal file
23
gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_insert_b (a, b, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_insert_b (a, b, 3);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_insert_b (a, b, 255);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.insert\\.b" 3 } } */
|
||||
23
gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c
Normal file
23
gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target cv_simd } */
|
||||
/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */
|
||||
|
||||
int
|
||||
foo1 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_insert_h (a, b, 0);
|
||||
}
|
||||
|
||||
int
|
||||
foo2 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_insert_h (a, b, 1);
|
||||
}
|
||||
|
||||
int
|
||||
foo3 (int a, int b)
|
||||
{
|
||||
return __builtin_riscv_cv_simd_insert_h (a, b, 255);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "cv\\.insert\\.h" 3 } } */
|
||||
1765
gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c
Normal file
1765
gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c
Normal file
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Add table
Reference in a new issue