Revert "AVX10.2 ymm rounding: Support vcvtph2{,u}w and vcvtps2p{d,hx} intrins"
This reverts commit b70bb94aca.
This commit is contained in:
Haochen Jiang
parent
08fd9bd48a
commit
567c939888
12 changed files with 1 additions and 304 deletions
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@ -726,143 +726,6 @@ _mm256_maskz_cvt_roundph_epu64 (__mmask8 __U, __m128h __A, const int __R)
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(__mmask8) __U,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundph_epu16 (__m256h __A, const int __R)
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{
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return
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(__m256i) __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) __A,
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(__v16hi)
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_mm256_undefined_si256 (),
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(__mmask16) -1,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundph_epu16 (__m256i __W, __mmask16 __U, __m256h __A,
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const int __R)
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{
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return (__m256i) __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) __A,
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(__v16hi) __W,
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(__mmask16) __U,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundph_epu16 (__mmask16 __U, __m256h __A, const int __R)
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{
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return
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(__m256i) __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) __A,
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(__v16hi)
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_mm256_setzero_si256 (),
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(__mmask16) __U,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundph_epi16 (__m256h __A, const int __R)
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{
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return
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(__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) __A,
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(__v16hi)
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_mm256_undefined_si256 (),
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(__mmask16) -1,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundph_epi16 (__m256i __W, __mmask16 __U, __m256h __A,
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const int __R)
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{
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return (__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) __A,
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(__v16hi) __W,
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(__mmask16) __U,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundph_epi16 (__mmask16 __U, __m256h __A, const int __R)
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{
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return
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(__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) __A,
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(__v16hi)
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_mm256_setzero_si256 (),
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(__mmask16) __U,
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__R);
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}
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extern __inline __m256d
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundps_pd (__m128 __A, const int __R)
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{
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return
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(__m256d) __builtin_ia32_vcvtps2pd256_mask_round ((__v4sf) __A,
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(__v4df)
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_mm256_undefined_pd (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m256d
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundps_pd (__m256d __W, __mmask8 __U, __m128 __A,
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const int __R)
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{
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return (__m256d) __builtin_ia32_vcvtps2pd256_mask_round ((__v4sf) __A,
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(__v4df) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m256d
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundps_pd (__mmask8 __U, __m128 __A, const int __R)
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{
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return (__m256d) __builtin_ia32_vcvtps2pd256_mask_round ((__v4sf) __A,
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(__v4df)
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_mm256_setzero_pd (),
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128h
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvtx_roundps_ph (__m256 __A, const int __R)
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{
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return (__m128h) __builtin_ia32_vcvtps2phx256_mask_round ((__v8sf) __A,
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(__v8hf)
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_mm_setzero_ph (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m128h
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvtx_roundps_ph (__m128h __W, __mmask8 __U, __m256 __A,
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const int __R)
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{
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return (__m128h) __builtin_ia32_vcvtps2phx256_mask_round ((__v8sf) __A,
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(__v8hf) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128h
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvtx_roundps_ph (__mmask8 __U, __m256 __A, const int __R)
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{
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return (__m128h) __builtin_ia32_vcvtps2phx256_mask_round ((__v8sf) __A,
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(__v8hf)
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_mm_setzero_ph (),
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(__mmask8) __U,
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__R);
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}
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#else
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#define _mm256_add_round_pd(A, B, R) \
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((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
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@ -1276,89 +1139,6 @@ _mm256_maskz_cvtx_roundps_ph (__mmask8 __U, __m256 __A, const int __R)
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(_mm256_setzero_si256 ()), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvt_roundph_epu16(A, R) \
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((__m256i) \
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__builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) (A), \
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(__v16hi) \
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(_mm256_undefined_si256 ()), \
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(__mmask16) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundph_epu16(W, U, A, R) \
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((__m256i) __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) (A), \
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(__v16hi) (W), \
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(__mmask16) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundph_epu16(U, A, R) \
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((__m256i) \
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__builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) (A), \
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(__v16hi) \
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(_mm256_setzero_si256 ()), \
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(__mmask16) (U), \
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(R)))
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#define _mm256_cvt_roundph_epi16(A, R) \
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((__m256i) \
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__builtin_ia32_vcvtph2w256_mask_round ((__v16hf) (A), \
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(__v16hi) \
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(_mm256_undefined_si256 ()), \
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(__mmask16) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundph_epi16(W, U, A, R) \
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((__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) (A), \
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(__v16hi) (W), \
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(__mmask16) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundph_epi16(U, A, R) \
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((__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) (A), \
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(__v16hi) \
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(_mm256_setzero_si256 ()), \
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(__mmask16) (U), \
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(R)))
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#define _mm256_cvt_roundps_pd(A, R) \
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((__m256d) __builtin_ia32_vcvtps2pd256_mask_round ((__v4sf) (A), \
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(__v4df) \
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(_mm256_undefined_pd ()), \
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundps_pd(W, U, A, R) \
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((__m256d) __builtin_ia32_vcvtps2pd256_mask_round ((__v4sf) (A), \
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(__v4df) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundps_pd(U, A, R) \
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((__m256d) __builtin_ia32_vcvtps2pd256_mask_round ((__v4sf) (A), \
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(__v4df) \
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(_mm256_setzero_pd ()), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvtx_roundps_ph(A, R) \
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((__m128h) __builtin_ia32_vcvtps2phx256_mask_round ((__v8sf) (A), \
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(__v8hf) \
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(_mm_setzero_ph ()), \
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvtx_roundps_ph(W, U, A, R) \
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((__m128h) __builtin_ia32_vcvtps2phx256_mask_round ((__v8sf) (A), \
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(__v8hf) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvtx_roundps_ph(U, A, R) \
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((__m128h) __builtin_ia32_vcvtps2phx256_mask_round ((__v8sf) (A), \
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(__v8hf) \
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(_mm_setzero_ph ()), \
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(__mmask8) (U), \
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(R)))
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#endif
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#ifdef __DISABLE_AVX10_2_256__
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@ -1432,9 +1432,6 @@ DEF_FUNCTION_TYPE (V8SI, V8HF, V8SI, UQI, INT)
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DEF_FUNCTION_TYPE (V4DF, V8HF, V4DF, UQI, INT)
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DEF_FUNCTION_TYPE (V8SF, V8HF, V8SF, UQI, INT)
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DEF_FUNCTION_TYPE (V4DI, V8HF, V4DI, UQI, INT)
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DEF_FUNCTION_TYPE (V16HI, V16HF, V16HI, UHI, INT)
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DEF_FUNCTION_TYPE (V4DF, V4SF, V4DF, UQI, INT)
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DEF_FUNCTION_TYPE (V8HF, V8SF, V8HF, UQI, INT)
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DEF_FUNCTION_TYPE (V32HF, V16SF, V16SF, V32HF, USI, INT)
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DEF_FUNCTION_TYPE (V32HF, V16SF, V16SF, V32HF, USI)
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DEF_FUNCTION_TYPE (V16HF, V8SF, V8SF, V16HF, UHI)
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@ -3681,10 +3681,6 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_float_extend_phv8sf2
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtph2qq_v4di_mask_round, "__builtin_ia32_vcvtph2qq256_mask_round", IX86_BUILTIN_VCVTPH2QQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V8HF_V4DI_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtph2udq_v8si_mask_round, "__builtin_ia32_vcvtph2udq256_mask_round", IX86_BUILTIN_VCVTPH2UDQ256_MASK_ROUND, UNKNOWN, (int) V8SI_FTYPE_V8HF_V8SI_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtph2uqq_v4di_mask_round, "__builtin_ia32_vcvtph2uqq256_mask_round", IX86_BUILTIN_VCVTPH2UQQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V8HF_V4DI_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtph2uw_v16hi_mask_round, "__builtin_ia32_vcvtph2uw256_mask_round", IX86_BUILTIN_VCVTPH2UW256_MASK_ROUND, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtph2w_v16hi_mask_round, "__builtin_ia32_vcvtph2w256_mask_round", IX86_BUILTIN_VCVTPH2W256_MASK_ROUND, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_cvtps2pd256_mask_round, "__builtin_ia32_vcvtps2pd256_mask_round", IX86_BUILTIN_VCVTPS2PD256_MASK_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtps2ph_v8sf_mask_round, "__builtin_ia32_vcvtps2phx256_mask_round", IX86_BUILTIN_VCVTPS2PHX256_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V8SF_V8HF_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvt2ps2phx_v32hf_mask_round, "__builtin_ia32_vcvt2ps2phx512_mask_round", IX86_BUILTIN_VCVT2PS2PHX_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V16SF_V16SF_V32HF_USI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtph2ibsv32hf_mask_round, "__builtin_ia32_cvtph2ibs512_mask_round", IX86_BUILTIN_CVTPH2IBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtph2iubsv32hf_mask_round, "__builtin_ia32_cvtph2iubs512_mask_round", IX86_BUILTIN_CVTPH2IUBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
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@ -12747,13 +12747,11 @@ ix86_expand_round_builtin (const struct builtin_description *d,
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case V16SI_FTYPE_V16SF_V16SI_UHI_INT:
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case V16SI_FTYPE_V16HF_V16SI_UHI_INT:
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case V16HF_FTYPE_V16SI_V16HF_UHI_INT:
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case V16HI_FTYPE_V16HF_V16HI_UHI_INT:
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case V8DF_FTYPE_V8SF_V8DF_QI_INT:
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case V16SF_FTYPE_V16HI_V16SF_HI_INT:
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case V8SF_FTYPE_V8SI_V8SF_UQI_INT:
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case V8SF_FTYPE_V8HF_V8SF_UQI_INT:
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case V8SI_FTYPE_V8HF_V8SI_UQI_INT:
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case V4DF_FTYPE_V4SF_V4DF_UQI_INT:
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case V4DF_FTYPE_V8HF_V4DF_UQI_INT:
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case V4DI_FTYPE_V8HF_V4DI_UQI_INT:
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case V4DI_FTYPE_V4DF_V4DI_UQI_INT:
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@ -12763,7 +12761,6 @@ ix86_expand_round_builtin (const struct builtin_description *d,
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case V4SF_FTYPE_V4SF_V4SF_V4SF_INT:
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case V8HF_FTYPE_V8DI_V8HF_UQI_INT:
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case V8HF_FTYPE_V8DF_V8HF_UQI_INT:
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case V8HF_FTYPE_V8SF_V8HF_UQI_INT:
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case V8HF_FTYPE_V8SI_V8HF_UQI_INT:
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case V8HF_FTYPE_V4DF_V8HF_UQI_INT:
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case V16HF_FTYPE_V16SF_V16HF_UHI_INT:
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@ -8109,7 +8109,7 @@
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[(set (match_operand:<ssePHmode> 0 "register_operand" "=v")
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(float_truncate:<ssePHmode>
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(match_operand:VF48H_AVX512VL 1 "<round_nimm_predicate>" "<round_constraint>")))]
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"TARGET_AVX512FP16 && <round_mode_condition>"
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"TARGET_AVX512FP16"
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"vcvt<castmode>2ph<ph2pssuffix><round_qq2phsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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@ -218,7 +218,6 @@
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|| <MODE>mode == V4DFmode
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|| <MODE>mode == V4DImode
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|| <MODE>mode == V8SImode
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|| <MODE>mode == V16HImode
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|| <MODE>mode == V16HFmode)))")
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(define_subst_attr "round_applied" "round" "false" "true")
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@ -864,10 +864,6 @@
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#define __builtin_ia32_vcvtph2qq256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2qq256_mask_round(A, B, C, 8)
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#define __builtin_ia32_vcvtph2udq256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2udq256_mask_round(A, B, C, 8)
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#define __builtin_ia32_vcvtph2uqq256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uqq256_mask_round(A, B, C, 8)
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#define __builtin_ia32_vcvtph2uw256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uw256_mask_round(A, B, C, 8)
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#define __builtin_ia32_vcvtph2w256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2w256_mask_round(A, B, C, 8)
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#define __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, 8)
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#define __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, 8)
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/* avx10_2-512mediaintrin.h */
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#define __builtin_ia32_mpsadbw512(A, B, C) __builtin_ia32_mpsadbw512 (A, B, 1)
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@ -60,18 +60,6 @@
|
|||
/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtps2pd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+\[^\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtps2pd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtps2pd\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtps2phxy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
|
|
@ -194,27 +182,3 @@ avx10_2_test_7 (void)
|
|||
x = _mm256_mask_cvtx_roundph_ps (x, m8, hxh, 8);
|
||||
x = _mm256_maskz_cvtx_roundph_ps (m8, hxh, 8);
|
||||
}
|
||||
|
||||
void extern
|
||||
avx10_2_test_8 (void)
|
||||
{
|
||||
xi = _mm256_cvt_roundph_epu16 (xh, 4);
|
||||
xi = _mm256_mask_cvt_roundph_epu16 (xi, m16, xh, 8);
|
||||
xi = _mm256_maskz_cvt_roundph_epu16 (m16, xh, 11);
|
||||
|
||||
xi = _mm256_cvt_roundph_epi16 (xh, 4);
|
||||
xi = _mm256_mask_cvt_roundph_epi16 (xi, m16, xh, 8);
|
||||
xi = _mm256_maskz_cvt_roundph_epi16 (m16, xh, 11);
|
||||
}
|
||||
|
||||
void extern
|
||||
avx10_2_test_9 (void)
|
||||
{
|
||||
xd = _mm256_cvt_roundps_pd (hx, _MM_FROUND_NO_EXC);
|
||||
xd = _mm256_mask_cvt_roundps_pd (xd, m8, hx, _MM_FROUND_NO_EXC);
|
||||
xd = _mm256_maskz_cvt_roundps_pd (m8, hx, _MM_FROUND_NO_EXC);
|
||||
|
||||
hxh = _mm256_cvtx_roundps_ph (x, 4);
|
||||
hxh = _mm256_mask_cvtx_roundps_ph (hxh, m8, x, 8);
|
||||
hxh = _mm256_maskz_cvtx_roundps_ph (m8, x, 11);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -871,10 +871,6 @@
|
|||
#define __builtin_ia32_vcvtph2qq256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2qq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtph2udq256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2udq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtph2uqq256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uqq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtph2uw256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uw256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtph2w256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2w256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, 8)
|
||||
|
||||
/* avx10_2-512mediaintrin.h */
|
||||
#define __builtin_ia32_mpsadbw512(A, B, C) __builtin_ia32_mpsadbw512 (A, B, 1)
|
||||
|
|
|
|||
|
|
@ -1035,10 +1035,6 @@ test_1 (_mm256_cvt_roundph_ps, __m256, __m128i, 8)
|
|||
test_1 (_mm256_cvtx_roundph_ps, __m256, __m128h, 8)
|
||||
test_1 (_mm256_cvt_roundph_epi64, __m256i, __m128h, 8)
|
||||
test_1 (_mm256_cvt_roundph_epu64, __m256i, __m128h, 8)
|
||||
test_1 (_mm256_cvt_roundph_epu16, __m256i, __m256h, 8)
|
||||
test_1 (_mm256_cvt_roundph_epi16, __m256i, __m256h, 8)
|
||||
test_1 (_mm256_cvt_roundps_pd, __m256d, __m128, 8)
|
||||
test_1 (_mm256_cvtx_roundps_ph, __m128h, __m256, 8)
|
||||
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
|
||||
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
|
||||
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
|
||||
|
|
@ -1057,10 +1053,6 @@ test_2 (_mm256_maskz_cvtx_roundph_ps, __m256, __mmask8, __m128h, 8)
|
|||
test_2 (_mm256_maskz_cvt_roundph_epi64, __m256i, __mmask8, __m128h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundph_epu32, __m256i, __mmask8, __m128h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundph_epu64, __m256i, __mmask8, __m128h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundph_epu16, __m256i, __mmask16, __m256h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundph_epi16, __m256i, __mmask16, __m256h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundps_pd, __m256d, __mmask8, __m128, 8)
|
||||
test_2 (_mm256_maskz_cvtx_roundps_ph, __m128h, __mmask8, __m256, 8)
|
||||
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
@ -1082,10 +1074,6 @@ test_3 (_mm256_mask_cvtx_roundph_ps, __m256, __m256, __mmask8, __m128h, 8)
|
|||
test_3 (_mm256_mask_cvt_roundph_epi64, __m256i, __m256i, __mmask8, __m128h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundph_epu32, __m256i, __m256i, __mmask8, __m128h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundph_epu64, __m256i, __m256i, __mmask8, __m128h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundph_epu16, __m256i, __m256i, __mmask16, __m256h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundph_epi16, __m256i, __m256i, __mmask16, __m256h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundps_pd, __m256d, __m256d, __mmask8, __m128, 8)
|
||||
test_3 (_mm256_mask_cvtx_roundps_ph, __m128h, __m128h, __mmask8, __m256, 8)
|
||||
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
|
|||
|
|
@ -1077,10 +1077,6 @@ test_1 (_mm256_cvtx_roundph_ps, __m256, __m128h, 8)
|
|||
test_1 (_mm256_cvt_roundph_epi64, __m256i, __m128h, 8)
|
||||
test_1 (_mm256_cvt_roundph_epu32, __m256i, __m128h, 8)
|
||||
test_1 (_mm256_cvt_roundph_epu64, __m256i, __m128h, 8)
|
||||
test_1 (_mm256_cvt_roundph_epu16, __m256i, __m256h, 8)
|
||||
test_1 (_mm256_cvt_roundph_epi16, __m256i, __m256h, 8)
|
||||
test_1 (_mm256_cvt_roundps_pd, __m256d, __m128, 8)
|
||||
test_1 (_mm256_cvtx_roundps_ph, __m128h, __m256, 8)
|
||||
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
|
||||
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
|
||||
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
|
||||
|
|
@ -1099,10 +1095,6 @@ test_2 (_mm256_maskz_cvtx_roundph_ps, __m256, __mmask8, __m128h, 8)
|
|||
test_2 (_mm256_maskz_cvt_roundph_epi64, __m256i, __mmask8, __m128h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundph_epu32, __m256i, __mmask8, __m128h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundph_epu64, __m256i, __mmask8, __m128h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundph_epu16, __m256i, __mmask16, __m256h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundph_epi16, __m256i, __mmask16, __m256h, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundps_pd, __m256d, __mmask8, __m128, 8)
|
||||
test_2 (_mm256_maskz_cvtx_roundps_ph, __m128h, __mmask8, __m256, 8)
|
||||
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
@ -1124,10 +1116,6 @@ test_3 (_mm256_mask_cvtx_roundph_ps, __m256, __m256, __mmask8, __m128h, 8)
|
|||
test_3 (_mm256_mask_cvt_roundph_epi64, __m256i, __m256i, __mmask8, __m128h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundph_epu32, __m256i, __m256i, __mmask8, __m128h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundph_epu64, __m256i, __m256i, __mmask8, __m128h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundph_epu16, __m256i, __m256i, __mmask16, __m256h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundph_epi16, __m256i, __m256i, __mmask16, __m256h, 8)
|
||||
test_3 (_mm256_mask_cvt_roundps_pd, __m256d, __m256d, __mmask8, __m128, 8)
|
||||
test_3 (_mm256_mask_cvtx_roundps_ph, __m128h, __m128h, __mmask8, __m256, 8)
|
||||
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
|
|||
|
|
@ -846,10 +846,6 @@
|
|||
#define __builtin_ia32_vcvtph2qq256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2qq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtph2udq256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2udq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtph2uqq256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uqq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtph2uw256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2uw256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtph2w256_mask_round(A, B, C, D) __builtin_ia32_vcvtph2w256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2pd256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, D) __builtin_ia32_vcvtps2phx256_mask_round(A, B, C, 8)
|
||||
|
||||
/* avx10_2-512mediaintrin.h */
|
||||
#define __builtin_ia32_mpsadbw512(A, B, C) __builtin_ia32_mpsadbw512 (A, B, 1)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue