i386.md (mul patterns): Allow memory operand to be first; add expanders where needed; fix constraints.
* i386.md (mul patterns): Allow memory operand to be first; add expanders where needed; fix constraints. (min?f_nonieee, max?f_nonieee, SSE TImode patterns): Allow memory operand to be the first. * i386.c (ix86_prepare_fp_compare_args): Fix condition for swapping operands. From-SVN: r49747
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
21117a1708
commit
558740bf3d
3 changed files with 215 additions and 62 deletions
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@ -1,3 +1,13 @@
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Wed Feb 13 23:34:30 CET 2002 Jan Hubicka <jh@suse.cz>
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* i386.md (mul patterns): Allow memory operand to be first;
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add expanders where needed; fix constraints.
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(min?f_nonieee, max?f_nonieee, SSE TImode patterns):
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Allow memory operand to be the first.
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* i386.c (ix86_prepare_fp_compare_args): Fix condition for swapping
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operands.
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2002-02-13 Jakub Jelinek <jakub@redhat.com>
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PR c/5681:
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@ -7137,7 +7137,7 @@ ix86_prepare_fp_compare_args (code, pop0, pop1)
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/* Try to rearrange the comparison to make it cheaper. */
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if (ix86_fp_comparison_cost (code)
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> ix86_fp_comparison_cost (swap_condition (code))
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&& (GET_CODE (op0) == REG || !reload_completed))
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&& (GET_CODE (op1) == REG || !no_new_pseudos))
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{
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rtx tmp;
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tmp = op0, op0 = op1, op1 = tmp;
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@ -7334,45 +7334,85 @@
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(set_attr "prefix_0f" "0,0,1")
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(set_attr "mode" "HI")])
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(define_insn "mulqi3"
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(define_expand "mulqi3"
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[(parallel [(set (match_operand:QI 0 "register_operand" "")
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(mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
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(match_operand:QI 2 "register_operand" "")))
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(clobber (reg:CC 17))])]
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"TARGET_QIMODE_MATH"
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"")
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(define_insn "*mulqi3_1"
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[(set (match_operand:QI 0 "register_operand" "=a")
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(mult:QI (match_operand:QI 1 "register_operand" "%0")
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(mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
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(match_operand:QI 2 "nonimmediate_operand" "qm")))
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(clobber (reg:CC 17))]
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"TARGET_QIMODE_MATH"
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"TARGET_QIMODE_MATH
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"mul{b}\t%2"
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[(set_attr "type" "imul")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "QI")])
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(define_insn "umulqihi3"
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(define_expand "umulqihi3"
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[(parallel [(set (match_operand:HI 0 "register_operand" "")
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(mult:HI (zero_extend:HI
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(match_operand:QI 1 "nonimmediate_operand" ""))
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(zero_extend:HI
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(match_operand:QI 2 "register_operand" ""))))
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(clobber (reg:CC 17))])]
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"TARGET_QIMODE_MATH"
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"")
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(define_insn "*umulqihi3_1"
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[(set (match_operand:HI 0 "register_operand" "=a")
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(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
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(mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
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(zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
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(clobber (reg:CC 17))]
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"TARGET_QIMODE_MATH"
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"TARGET_QIMODE_MATH
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"mul{b}\t%2"
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[(set_attr "type" "imul")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "QI")])
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(define_insn "mulqihi3"
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(define_expand "mulqihi3"
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[(parallel [(set (match_operand:HI 0 "register_operand" "")
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(mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
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(sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
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(clobber (reg:CC 17))])]
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"TARGET_QIMODE_MATH"
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"")
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(define_insn "*mulqihi3_insn"
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[(set (match_operand:HI 0 "register_operand" "=a")
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(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
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(mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
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(sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
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(clobber (reg:CC 17))]
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"TARGET_QIMODE_MATH"
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"TARGET_QIMODE_MATH
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"imul{b}\t%2"
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[(set_attr "type" "imul")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "QI")])
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(define_insn "umulditi3"
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(define_expand "umulditi3"
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[(parallel [(set (match_operand:TI 0 "register_operand" "")
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(mult:TI (zero_extend:TI
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(match_operand:DI 1 "nonimmediate_operand" ""))
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(zero_extend:TI
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(match_operand:DI 2 "register_operand" ""))))
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(clobber (reg:CC 17))])]
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"TARGET_64BIT"
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"")
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(define_insn "*umulditi3_insn"
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[(set (match_operand:TI 0 "register_operand" "=A")
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(mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
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(mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
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(zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
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(clobber (reg:CC 17))]
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"TARGET_64BIT"
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"TARGET_64BIT
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"mul{q}\t%2"
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[(set_attr "type" "imul")
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(set_attr "ppro_uops" "few")
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@ -7380,70 +7420,132 @@
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(set_attr "mode" "DI")])
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;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
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(define_insn "umulsidi3"
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(define_expand "umulsidi3"
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[(parallel [(set (match_operand:DI 0 "register_operand" "")
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(mult:DI (zero_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" ""))
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(zero_extend:DI
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(match_operand:SI 2 "register_operand" ""))))
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(clobber (reg:CC 17))])]
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"!TARGET_64BIT"
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"")
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(define_insn "*umulsidi3_insn"
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[(set (match_operand:DI 0 "register_operand" "=A")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
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(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
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(zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
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(clobber (reg:CC 17))]
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"!TARGET_64BIT"
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"!TARGET_64BIT
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"mul{l}\t%2"
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[(set_attr "type" "imul")
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(set_attr "ppro_uops" "few")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "SI")])
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(define_insn "mulditi3"
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(define_expand "mulditi3"
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[(parallel [(set (match_operand:TI 0 "register_operand" "")
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(mult:TI (sign_extend:TI
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(match_operand:DI 1 "nonimmediate_operand" ""))
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(sign_extend:TI
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(match_operand:DI 2 "register_operand" ""))))
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(clobber (reg:CC 17))])]
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"TARGET_64BIT"
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"")
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(define_insn "*mulditi3_insn"
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[(set (match_operand:TI 0 "register_operand" "=A")
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(mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
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(mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
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(sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
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(clobber (reg:CC 17))]
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"TARGET_64BIT"
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"TARGET_64BIT
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"imul{q}\t%2"
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[(set_attr "type" "imul")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "DI")])
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(define_insn "mulsidi3"
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(define_expand "mulsidi3"
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[(parallel [(set (match_operand:DI 0 "register_operand" "")
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(mult:DI (sign_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" ""))
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(sign_extend:DI
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(match_operand:SI 2 "register_operand" ""))))
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(clobber (reg:CC 17))])]
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"!TARGET_64BIT"
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"")
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(define_insn "*mulsidi3_insn"
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[(set (match_operand:DI 0 "register_operand" "=A")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
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(mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
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(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
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(clobber (reg:CC 17))]
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"!TARGET_64BIT"
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"!TARGET_64BIT
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"imul{l}\t%2"
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[(set_attr "type" "imul")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "SI")])
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(define_expand "umuldi3_highpart"
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[(parallel [(set (match_operand:DI 0 "register_operand" "")
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(truncate:DI
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(lshiftrt:TI
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(mult:TI (zero_extend:TI
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(match_operand:DI 1 "nonimmediate_operand" ""))
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(zero_extend:TI
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(match_operand:DI 2 "register_operand" "")))
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(const_int 64))))
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(clobber (match_scratch:DI 3 ""))
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(clobber (reg:CC 17))])]
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"TARGET_64BIT"
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"")
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(define_insn "*umuldi3_highpart_rex64"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(truncate:DI
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(lshiftrt:TI
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(mult:TI (zero_extend:TI
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(match_operand:DI 1 "register_operand" "%a"))
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(match_operand:DI 1 "nonimmediate_operand" "%a"))
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(zero_extend:TI
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(match_operand:DI 2 "nonimmediate_operand" "rm")))
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(const_int 64))))
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(clobber (match_scratch:DI 3 "=a"))
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(clobber (match_scratch:DI 3 "=1"))
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(clobber (reg:CC 17))]
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"TARGET_64BIT"
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"TARGET_64BIT
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"mul{q}\t%2"
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[(set_attr "type" "imul")
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(set_attr "ppro_uops" "few")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "DI")])
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(define_insn "umulsi3_highpart"
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(define_expand "umulsi3_highpart"
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(truncate:SI
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(lshiftrt:DI
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(mult:DI (zero_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" ""))
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(zero_extend:DI
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(match_operand:SI 2 "register_operand" "")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 ""))
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(clobber (reg:CC 17))])]
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""
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"")
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(define_insn "*umulsi3_highpart_insn"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(truncate:SI
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(lshiftrt:DI
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(mult:DI (zero_extend:DI
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(match_operand:SI 1 "register_operand" "%a"))
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(match_operand:SI 1 "nonimmediate_operand" "%a"))
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(zero_extend:DI
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(match_operand:SI 2 "nonimmediate_operand" "rm")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=a"))
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(clobber (match_scratch:SI 3 "=1"))
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(clobber (reg:CC 17))]
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""
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"GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
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"mul{l}\t%2"
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[(set_attr "type" "imul")
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(set_attr "ppro_uops" "few")
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@ -7455,48 +7557,78 @@
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(zero_extend:DI (truncate:SI
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(lshiftrt:DI
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(mult:DI (zero_extend:DI
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(match_operand:SI 1 "register_operand" "%a"))
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(match_operand:SI 1 "nonimmediate_operand" "%a"))
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(zero_extend:DI
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(match_operand:SI 2 "nonimmediate_operand" "rm")))
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(const_int 32)))))
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(clobber (match_scratch:SI 3 "=a"))
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(clobber (match_scratch:SI 3 "=1"))
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(clobber (reg:CC 17))]
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"TARGET_64BIT"
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"TARGET_64BIT
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"mul{l}\t%2"
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[(set_attr "type" "imul")
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(set_attr "ppro_uops" "few")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "SI")])
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(define_expand "smuldi3_highpart"
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[(parallel [(set (match_operand:DI 0 "register_operand" "=d")
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(truncate:DI
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(lshiftrt:TI
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(mult:TI (sign_extend:TI
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(match_operand:DI 1 "nonimmediate_operand" ""))
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(sign_extend:TI
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(match_operand:DI 2 "register_operand" "")))
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(const_int 64))))
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(clobber (match_scratch:DI 3 ""))
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(clobber (reg:CC 17))])]
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"TARGET_64BIT"
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"")
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(define_insn "*smuldi3_highpart_rex64"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(truncate:DI
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(lshiftrt:TI
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(mult:TI (sign_extend:TI
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(match_operand:DI 1 "register_operand" "%a"))
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(match_operand:DI 1 "nonimmediate_operand" "%a"))
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(sign_extend:TI
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(match_operand:DI 2 "nonimmediate_operand" "rm")))
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(const_int 64))))
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(clobber (match_scratch:DI 3 "=a"))
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(clobber (match_scratch:DI 3 "=1"))
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(clobber (reg:CC 17))]
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"TARGET_64BIT"
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"TARGET_64BIT
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"imul{q}\t%2"
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[(set_attr "type" "imul")
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(set_attr "ppro_uops" "few")
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(set_attr "mode" "DI")])
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|
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(define_insn "smulsi3_highpart"
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(define_expand "smulsi3_highpart"
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(truncate:SI
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(lshiftrt:DI
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(mult:DI (sign_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" ""))
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(sign_extend:DI
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(match_operand:SI 2 "register_operand" "")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 ""))
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(clobber (reg:CC 17))])]
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""
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"")
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||||
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(define_insn "*smulsi3_highpart_insn"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(truncate:SI
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||||
(lshiftrt:DI
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(mult:DI (sign_extend:DI
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||||
(match_operand:SI 1 "register_operand" "%a"))
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(match_operand:SI 1 "nonimmediate_operand" "%a"))
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||||
(sign_extend:DI
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||||
(match_operand:SI 2 "nonimmediate_operand" "rm")))
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||||
(const_int 32))))
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||||
(clobber (match_scratch:SI 3 "=a"))
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(clobber (match_scratch:SI 3 "=1"))
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||||
(clobber (reg:CC 17))]
|
||||
""
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||||
"GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
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||||
"imul{l}\t%2"
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||||
[(set_attr "type" "imul")
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(set_attr "ppro_uops" "few")
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|
|
@ -7507,13 +7639,14 @@
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(zero_extend:DI (truncate:SI
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||||
(lshiftrt:DI
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||||
(mult:DI (sign_extend:DI
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||||
(match_operand:SI 1 "register_operand" "%a"))
|
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(match_operand:SI 1 "nonimmediate_operand" "%a"))
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||||
(sign_extend:DI
|
||||
(match_operand:SI 2 "nonimmediate_operand" "rm")))
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||||
(const_int 32)))))
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||||
(clobber (match_scratch:SI 3 "=a"))
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||||
(clobber (match_scratch:SI 3 "=1"))
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||||
(clobber (reg:CC 17))]
|
||||
"TARGET_64BIT"
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||||
"TARGET_64BIT
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||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"imul{l}\t%2"
|
||||
[(set_attr "type" "imul")
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||||
(set_attr "ppro_uops" "few")
|
||||
|
|
@ -15975,12 +16108,13 @@
|
|||
|
||||
(define_insn "*minsf_nonieee"
|
||||
[(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
|
||||
(if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
|
||||
(if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
|
||||
(match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_SSE && !TARGET_IEEE_FP"
|
||||
"TARGET_SSE && !TARGET_IEEE_FP
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"#")
|
||||
|
||||
(define_split
|
||||
|
|
@ -16057,12 +16191,13 @@
|
|||
|
||||
(define_insn "*mindf_nonieee"
|
||||
[(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
|
||||
(if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
|
||||
(if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
|
||||
(match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"#")
|
||||
|
||||
(define_split
|
||||
|
|
@ -16138,12 +16273,13 @@
|
|||
|
||||
(define_insn "*maxsf_nonieee"
|
||||
[(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
|
||||
(if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
|
||||
(if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
|
||||
(match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_SSE && !TARGET_IEEE_FP"
|
||||
"TARGET_SSE && !TARGET_IEEE_FP
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"#")
|
||||
|
||||
(define_split
|
||||
|
|
@ -16218,12 +16354,13 @@
|
|||
|
||||
(define_insn "*maxdf_nonieee"
|
||||
[(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
|
||||
(if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
|
||||
(if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
|
||||
(match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"#")
|
||||
|
||||
(define_split
|
||||
|
|
@ -18239,17 +18376,19 @@
|
|||
|
||||
(define_insn "sse_andti3"
|
||||
[(set (match_operand:TI 0 "register_operand" "=x")
|
||||
(and:TI (match_operand:TI 1 "register_operand" "%0")
|
||||
(and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
|
||||
"TARGET_SSE && !TARGET_SSE2"
|
||||
"TARGET_SSE && !TARGET_SSE2
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"andps\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sse")])
|
||||
|
||||
(define_insn "*sse_andti3_sse2"
|
||||
[(set (match_operand:TI 0 "register_operand" "=x")
|
||||
(and:TI (match_operand:TI 1 "register_operand" "%0")
|
||||
(and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
|
||||
"TARGET_SSE2"
|
||||
"TARGET_SSE2
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"pand\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sse")])
|
||||
|
||||
|
|
@ -18319,17 +18458,19 @@
|
|||
|
||||
(define_insn "sse_iorti3"
|
||||
[(set (match_operand:TI 0 "register_operand" "=x")
|
||||
(ior:TI (match_operand:TI 1 "register_operand" "%0")
|
||||
(ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
|
||||
"TARGET_SSE && !TARGET_SSE2"
|
||||
"TARGET_SSE && !TARGET_SSE2
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"orps\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sse")])
|
||||
|
||||
(define_insn "*sse_iorti3_sse2"
|
||||
[(set (match_operand:TI 0 "register_operand" "=x")
|
||||
(ior:TI (match_operand:TI 1 "register_operand" "%0")
|
||||
(ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
|
||||
"TARGET_SSE2"
|
||||
"TARGET_SSE2
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"por\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sse")])
|
||||
|
||||
|
|
@ -18367,17 +18508,19 @@
|
|||
|
||||
(define_insn "sse_xorti3"
|
||||
[(set (match_operand:TI 0 "register_operand" "=x")
|
||||
(xor:TI (match_operand:TI 1 "register_operand" "%0")
|
||||
(xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
|
||||
"TARGET_SSE && !TARGET_SSE2"
|
||||
"TARGET_SSE && !TARGET_SSE2
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"xorps\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sse")])
|
||||
|
||||
(define_insn "*sse_xorti3_sse2"
|
||||
[(set (match_operand:TI 0 "register_operand" "=x")
|
||||
(xor:TI (match_operand:TI 1 "register_operand" "%0")
|
||||
(xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
|
||||
"TARGET_SSE2"
|
||||
"TARGET_SSE2
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"pxor\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sse")])
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue