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i386: Use ix86_output_ssemov for MMX TYPE_SSEMOV

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There is no need to set mode attribute to XImode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.

	PR target/89229
	* config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
	MODE_V1DF and MODE_V2SF.
	* config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
	ix86_output_ssemov for TYPE_SSEMOV.  Remove ext_sse_reg_operand
	check.
This commit is contained in:
H.J. Lu 2020-03-12 03:47:45 -07:00
parent 98aeb1ef51
commit 54f46d82f5
3 changed files with 30 additions and 27 deletions
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9
gcc/ChangeLog
View file

@ -1,3 +1,12 @@
2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
PR target/89229
* config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
MODE_V1DF and MODE_V2SF.
* config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
check.
2020-03-12 Jakub Jelinek <jakub@redhat.com>
* doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change

19
gcc/config/i386/i386.c
View file

@ -5118,6 +5118,25 @@ ix86_output_ssemov (rtx_insn *insn, rtx *operands)
case MODE_V4SF:
return ix86_get_ssemov (operands, 16, insn_mode, mode);
case MODE_DI:
/* Handle broken assemblers that require movd instead of movq. */
if (!HAVE_AS_IX86_INTERUNIT_MOVQ
&& (GENERAL_REG_P (operands[0])
|| GENERAL_REG_P (operands[1])))
return "%vmovd\t{%1, %0|%0, %1}";
else
return "%vmovq\t{%1, %0|%0, %1}";
case MODE_V1DF:
gcc_assert (!TARGET_AVX);
return "movlpd\t{%1, %0|%0, %1}";
case MODE_V2SF:
if (TARGET_AVX && REG_P (operands[0]))
return "vmovlps\t{%1, %d0|%d0, %1}";
else
return "%vmovlps\t{%1, %0|%0, %1}";
default:
gcc_unreachable ();
}

29
gcc/config/i386/mmx.md
View file

@ -118,29 +118,7 @@
return standard_sse_constant_opcode (insn, operands);
case TYPE_SSEMOV:
switch (get_attr_mode (insn))
{
case MODE_DI:
/* Handle broken assemblers that require movd instead of movq. */
if (!HAVE_AS_IX86_INTERUNIT_MOVQ
&& (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
return "%vmovd\t{%1, %0|%0, %1}";
return "%vmovq\t{%1, %0|%0, %1}";
case MODE_TI:
return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_XI:
return "vmovdqa64\t{%g1, %g0|%g0, %g1}";
case MODE_V2SF:
if (TARGET_AVX && REG_P (operands[0]))
return "vmovlps\t{%1, %0, %0|%0, %0, %1}";
return "%vmovlps\t{%1, %0|%0, %1}";
case MODE_V4SF:
return "%vmovaps\t{%1, %0|%0, %1}";
default:
gcc_unreachable ();
}
return ix86_output_ssemov (insn, operands);
default:
gcc_unreachable ();
@ -189,10 +167,7 @@
(cond [(eq_attr "alternative" "2")
(const_string "SI")
(eq_attr "alternative" "11,12")
(cond [(ior (match_operand 0 "ext_sse_reg_operand")
(match_operand 1 "ext_sse_reg_operand"))
(const_string "XI")
(match_test "<MODE>mode == V2SFmode")
(cond [(match_test "<MODE>mode == V2SFmode")
(const_string "V4SF")
(ior (not (match_test "TARGET_SSE2"))
(match_test "optimize_function_for_size_p (cfun)"))