re PR target/15184 (Direct access to byte inside word not working with -march=pentiumpro)
PR target/15184 * combine.c (try_combine): If I0 is a memory load and I3 a store to a related address, increase the "goodness" of doing a 4-insn combination with I0-I3. (make_field_assignment): Handle SUBREGs in the ior+and case. PR target/15184 * gcc.target/i386/pr15184-1.c: New test. * gcc.target/i386/pr15184-2.c: New test. From-SVN: r220249
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Jeff Law
Jeff Law
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5 changed files with 134 additions and 0 deletions
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@ -1,3 +1,11 @@
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2015-01-29 Jeff Law <law@redhat.com>
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PR target/15184
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* combine.c (try_combine): If I0 is a memory load and I3 a store
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to a related address, increase the "goodness" of doing a 4-insn
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combination with I0-I3.
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(make_field_assignment): Handle SUBREGs in the ior+and case.
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2015-01-29 Yuri Rumyantsev <ysrumyan@gmail.com>
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PR tree-optimization/64746
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@ -2620,6 +2620,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
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int i;
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int ngood = 0;
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int nshift = 0;
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rtx set0, set3;
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if (!flag_expensive_optimizations)
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return 0;
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@ -2643,6 +2644,34 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
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|| GET_CODE (src) == LSHIFTRT)
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nshift++;
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}
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/* If I0 loads a memory and I3 sets the same memory, then I2 and I3
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are likely manipulating its value. Ideally we'll be able to combine
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all four insns into a bitfield insertion of some kind.
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Note the source in I0 might be inside a sign/zero extension and the
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memory modes in I0 and I3 might be different. So extract the address
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from the destination of I3 and search for it in the source of I0.
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In the event that there's a match but the source/dest do not actually
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refer to the same memory, the worst that happens is we try some
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combinations that we wouldn't have otherwise. */
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if ((set0 = single_set (i0))
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/* Ensure the source of SET0 is a MEM, possibly buried inside
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an extension. */
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&& (GET_CODE (SET_SRC (set0)) == MEM
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|| ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
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|| GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
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&& GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
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&& (set3 = single_set (i3))
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/* Ensure the destination of SET3 is a MEM. */
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&& GET_CODE (SET_DEST (set3)) == MEM
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/* Would it be better to extract the base address for the MEM
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in SET3 and look for that? I don't have cases where it matters
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but I could envision such cases. */
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&& rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
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ngood += 2;
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if (ngood < 2 && nshift < 2)
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return 0;
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}
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@ -9272,6 +9301,13 @@ make_field_assignment (rtx x)
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to the appropriate position, force it to the required mode, and
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make the extraction. Check for the AND in both operands. */
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/* One or more SUBREGs might obscure the constant-position field
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assignment. The first one we are likely to encounter is an outer
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narrowing SUBREG, which we can just strip for the purposes of
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identifying the constant-field assignment. */
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if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))
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src = SUBREG_REG (src);
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if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
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return x;
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@ -9282,10 +9318,38 @@ make_field_assignment (rtx x)
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&& CONST_INT_P (XEXP (rhs, 1))
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&& rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
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c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
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/* The second SUBREG that might get in the way is a paradoxical
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SUBREG around the first operand of the AND. We want to
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pretend the operand is as wide as the destination here. We
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do this by creating a new MEM in the wider mode for the sole
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purpose of the call to rtx_equal_for_field_assignment_p. Also
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note this trick only works for MEMs. */
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else if (GET_CODE (rhs) == AND
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&& paradoxical_subreg_p (XEXP (rhs, 0))
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&& GET_CODE (SUBREG_REG (XEXP (rhs, 0))) == MEM
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&& CONST_INT_P (XEXP (rhs, 1))
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&& rtx_equal_for_field_assignment_p (gen_rtx_MEM (GET_MODE (dest),
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XEXP (SUBREG_REG (XEXP (rhs, 0)), 0)),
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dest))
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c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
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else if (GET_CODE (lhs) == AND
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&& CONST_INT_P (XEXP (lhs, 1))
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&& rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
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c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
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/* The second SUBREG that might get in the way is a paradoxical
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SUBREG around the first operand of the AND. We want to
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pretend the operand is as wide as the destination here. We
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do this by creating a new MEM in the wider mode for the sole
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purpose of the call to rtx_equal_for_field_assignment_p. Also
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note this trick only works for MEMs. */
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else if (GET_CODE (lhs) == AND
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&& paradoxical_subreg_p (XEXP (lhs, 0))
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&& GET_CODE (SUBREG_REG (XEXP (lhs, 0))) == MEM
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&& CONST_INT_P (XEXP (lhs, 1))
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&& rtx_equal_for_field_assignment_p (gen_rtx_MEM (GET_MODE (dest),
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XEXP (SUBREG_REG (XEXP (lhs, 0)), 0)),
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dest))
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c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
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else
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return x;
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@ -1,3 +1,9 @@
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2015-01-29 Jeff Law <law@redhat.com>
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PR target/15184
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* gcc.target/i386/pr15184-1.c: New test.
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* gcc.target/i386/pr15184-2.c: New test.
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2015-01-29 Yuri Rumyantsev <ysrumyan@gmail.com>
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PR tree-optimization/64746
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33
gcc/testsuite/gcc.target/i386/pr15184-1.c
Normal file
33
gcc/testsuite/gcc.target/i386/pr15184-1.c
Normal file
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@ -0,0 +1,33 @@
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/* PR 15184 first two tests, plus two addition ones. */
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/* { dg-do compile } */
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/* { dg-options "-O2 -m32 -march=pentiumpro" } */
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#define regparm __attribute__((__regparm__(3)))
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extern unsigned int x;
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extern unsigned short y;
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void regparm f0(unsigned char c)
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{
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x = (x & 0xFFFFFF00) | (unsigned int)c;
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}
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void regparm f1(unsigned char c)
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{
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x = (x & 0xFFFF00FF) | ((unsigned int)c << 8);
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}
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void regparm f2(unsigned char c)
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{
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x = (x & 0xFF00FFFF) | ((unsigned int)c << 16);
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}
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void regparm f3(unsigned char c)
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{
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x = (x & 0x00FFFFFF) | ((unsigned int)c << 24);
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}
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/* Each function should compile down to a byte move from
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the input register into x, possibly at an offset within x. */
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/* { dg-final { scan-assembler-times "\tmovb\t%al, x" 4 } } */
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23
gcc/testsuite/gcc.target/i386/pr15184-2.c
Normal file
23
gcc/testsuite/gcc.target/i386/pr15184-2.c
Normal file
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@ -0,0 +1,23 @@
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/* PR 15184 second two tests
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/* { dg-do compile } */
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/* { dg-options "-O2 -m32 -march=pentiumpro" } */
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#define regparm __attribute__((__regparm__(3)))
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extern unsigned int x;
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extern unsigned short y;
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void regparm g0(unsigned char c)
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{
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y = (y & 0xFF00) | (unsigned short)c;
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}
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void regparm g1(unsigned char c)
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{
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y = (y & 0x00FF) | ((unsigned short)c << 8);
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}
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/* Each function should compile down to a byte move from
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the input register into x, possibly at an offset within x. */
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/* { dg-final { scan-assembler-times "\tmovb\t%al, y" 2 } } */
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