2084.md: New file.
* config/s390/2084.md: New file. * config/s390/s390.md: Include it. * config/s390/s390.c (s390_adjust_priority): New function. (TARGET_SCHED_ADJUST_PRIORITY): Define. (s390_first_cycle_multipass_dfa_lookahead): New function. (TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Define. (s390_sched_reorder2): New function. (TARGET_SCHED_REORDER2): Define. (s390_adjust_cost): Support PROCESSOR_2084_Z990 cpu type. (s390_issue_rate): Likewise. Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com> From-SVN: r68743
This commit is contained in:
Hartmut Penner
Ulrich Weigand
parent
ed2df68b4b
commit
52609473f8
4 changed files with 356 additions and 5 deletions
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@ -1,3 +1,17 @@
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2003-06-30 Hartmut Penner <hpenner@de.ibm.com>
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Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/2084.md: New file.
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* config/s390/s390.md: Include it.
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* config/s390/s390.c (s390_adjust_priority): New function.
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(TARGET_SCHED_ADJUST_PRIORITY): Define.
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(s390_first_cycle_multipass_dfa_lookahead): New function.
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(TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Define.
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(s390_sched_reorder2): New function.
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(TARGET_SCHED_REORDER2): Define.
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(s390_adjust_cost): Support PROCESSOR_2084_Z990 cpu type.
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(s390_issue_rate): Likewise.
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Mon Jun 30 23:47:33 CEST 2003 Jan Hubicka <jh@suse.cz>
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* Makefile.in (GTFILES): Add cgraph.h.
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262
gcc/config/s390/2084.md
Normal file
262
gcc/config/s390/2084.md
Normal file
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@ -0,0 +1,262 @@
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;; Scheduling description for z990 (cpu 2084).
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;; Copyright (C) 2003 Free Software Foundation, Inc.
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;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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;; Ulrich Weigand (uweigand@de.ibm.com).
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;;
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;; This file is part of GNU CC.
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;;
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;; GNU CC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GNU CC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GNU CC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 59 Temple Place - Suite 330,
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;; Boston, MA 02111-1307, USA.
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(define_automaton "x_ipu")
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(define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu")
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(define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu")
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(define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu")
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(define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu")
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(define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu")
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(define_cpu_unit "x_store_tok" "x_ipu")
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(define_cpu_unit "x_ms,x_mt" "x_ipu")
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(define_reservation "x-e1-st" "(x_e1_s | x_e1_t)")
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(define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)")
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(absence_set "x_e1_r" "x_e1_s,x_e1_t")
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(absence_set "x_e1_s" "x_e1_t")
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;; Try to avoid int <-> fp transitions.
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(define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4")
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(define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6")
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(define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)")
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(define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)")
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(define_reservation "x-wr-fp" "x_wr_fp,x-f")
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(define_reservation "x-mem" "x_ms|x_mt")
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(absence_set "x_wr_fp"
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"x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t")
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(absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t"
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"x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp")
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;; Don't have any load type insn in same group as store
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(absence_set "x_ms,x_mt" "x_store_tok")
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;;
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;; Simple insns
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;;
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(define_insn_reservation "x_lr" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "lr"))
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"x-e1-st,x-wr-st")
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(define_insn_reservation "x_la" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "la"))
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"x-e1-st,x-wr-st")
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(define_insn_reservation "x_larl" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "larl"))
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"x-e1-st,x-wr-st")
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(define_insn_reservation "x_load" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "load"))
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"x-e1-st+x-mem,x-wr-st")
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(define_insn_reservation "x_store" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "store"))
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"x-e1-st+x_store_tok,x-wr-st")
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(define_insn_reservation "x_branch" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "branch"))
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"x_e1_r,x_wr_r")
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(define_insn_reservation "x_call" 5
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "jsr"))
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"x-e1-np*5,x-wr-np")
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;;
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;; Multicycle insns
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;;
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(define_insn_reservation "x_ss" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "op_type" "SS"))
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"x-e1-np,x-wr-np")
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(define_insn_reservation "x_stm" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "stm"))
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"(x-e1-np+x_store_tok)*10,x-wr-np")
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(define_insn_reservation "x_lm" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "lm"))
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"x-e1-np*10,x-wr-np")
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(define_insn_reservation "x_nn" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "op_type" "NN"))
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"x-e1-np,x-wr-np")
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(define_insn_reservation "x_o2" 2
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "o2"))
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"x-e1-np*2,x-wr-np")
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(define_insn_reservation "x_o3" 3
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "o3"))
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"x-e1-np*3,x-wr-np")
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;;
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;; Floating point insns
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;;
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(define_insn_reservation "x_fsimpd" 6
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fsimpd,fmuld"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_fsimps" 6
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fsimps,fmuls"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_fdivd" 36
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fdivd"))
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"x_e1_t*30,x-wr-fp")
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(define_insn_reservation "x_fdivs" 36
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fdivs"))
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"x_e1_t*30,x-wr-fp")
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(define_insn_reservation "x_floadd" 6
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "floadd"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_floads" 6
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "floads"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_fstored" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fstored"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_fstores" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fstores"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_ftoi" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "ftoi"))
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"x_e1_t*3,x-wr-fp")
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(define_insn_reservation "x_itof" 7
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "itof"))
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"x_e1_t*3,x-wr-fp")
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(define_bypass 1 "x_fsimpd" "x_fstored")
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(define_bypass 1 "x_fsimps" "x_fstores")
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(define_bypass 1 "x_floadd" "x_fsimpd,x_fstored,x_floadd")
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(define_bypass 1 "x_floads" "x_fsimps,x_fstores,x_floads")
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;;
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;; Insns still not mentioned are checked for
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;; the usage of the agen unit
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;;
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(define_insn_reservation "x_int" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "atype" "reg"))
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"x-e1-st,x-wr-st")
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(define_insn_reservation "x_agen" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "atype" "agen"))
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"x-e1-st+x-mem,x-wr-st")
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;;
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;; s390_agen_dep_p returns 1, if a register is set in the
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;; first insn and used in the dependend insn to form a address.
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;;
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;;
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;; If a intruction uses a register to address memory, it needs
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;; to be set 5 cycles in advance.
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;;
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(define_bypass 5 "x_int,x_agen,x_lr"
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"x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
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"s390_agen_dep_p")
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(define_bypass 9 "x_int,x_agen,x_lr"
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"x_floadd, x_floads, x_fstored, x_fstores,\
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x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
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"s390_agen_dep_p")
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;;
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;; A load type instruction uses a bypass to feed the result back
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;; to the address generation pipeline stage.
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;;
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(define_bypass 4 "x_load"
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"x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
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"s390_agen_dep_p")
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(define_bypass 5 "x_load"
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"x_floadd, x_floads, x_fstored, x_fstores,\
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x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
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"s390_agen_dep_p")
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;;
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;; A load address type instruction uses a bypass to feed the
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;; result back to the address generation pipeline stage.
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;;
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(define_bypass 3 "x_larl,x_la"
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"x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
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"s390_agen_dep_p")
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(define_bypass 5 "x_larl, x_la"
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"x_floadd, x_floads, x_fstored, x_fstores,\
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x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
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"s390_agen_dep_p")
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;;
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;; Operand forwarding
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;;
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(define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr")
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@ -68,12 +68,16 @@ static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
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static enum attr_type s390_safe_attr_type PARAMS ((rtx));
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static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int));
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static int s390_adjust_priority PARAMS ((rtx, int));
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static int s390_issue_rate PARAMS ((void));
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static int s390_use_dfa_pipeline_interface PARAMS ((void));
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static int s390_first_cycle_multipass_dfa_lookahead PARAMS ((void));
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static int s390_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
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static bool s390_rtx_costs PARAMS ((rtx, int, int, int *));
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static int s390_address_cost PARAMS ((rtx));
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static void s390_reorg PARAMS ((void));
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#undef TARGET_ASM_ALIGNED_HI_OP
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#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
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#undef TARGET_ASM_ALIGNED_DI_OP
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@ -115,10 +119,16 @@ static void s390_reorg PARAMS ((void));
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#undef TARGET_SCHED_ADJUST_COST
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#define TARGET_SCHED_ADJUST_COST s390_adjust_cost
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#undef TARGET_SCHED_ADJUST_PRIORITY
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#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
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#undef TARGET_SCHED_ISSUE_RATE
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#define TARGET_SCHED_ISSUE_RATE s390_issue_rate
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#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
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#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE s390_use_dfa_pipeline_interface
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#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
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#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
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#undef TARGET_SCHED_REORDER2
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#define TARGET_SCHED_REORDER2 s390_sched_reorder2
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#undef TARGET_RTX_COSTS
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#define TARGET_RTX_COSTS s390_rtx_costs
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@ -3611,7 +3621,6 @@ addr_generation_dependency_p (dep_rtx, insn)
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/* Return 1, if dep_insn sets register used in insn in the agen unit. */
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int
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s390_agen_dep_p(dep_insn, insn)
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rtx dep_insn;
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@ -3634,7 +3643,6 @@ s390_agen_dep_p(dep_insn, insn)
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return 0;
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}
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/* Return the modified cost of the dependency of instruction INSN
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on instruction DEP_INSN through the link LINK. COST is the
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default cost of that dependency.
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@ -3669,7 +3677,16 @@ s390_adjust_cost (insn, link, dep_insn, cost)
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/* DFA based scheduling checks address dependency in md file. */
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if (s390_use_dfa_pipeline_interface ())
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return cost;
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{
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/* Operand forward in case of lr, load and la. */
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if (s390_tune == PROCESSOR_2084_Z990
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&& cost == 1
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&& (s390_safe_attr_type (dep_insn) == TYPE_LA
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|| s390_safe_attr_type (dep_insn) == TYPE_LR
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|| s390_safe_attr_type (dep_insn) == TYPE_LOAD))
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return 0;
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return cost;
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}
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dep_rtx = PATTERN (dep_insn);
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@ -3687,12 +3704,47 @@ s390_adjust_cost (insn, link, dep_insn, cost)
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return cost;
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}
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/* A C statement (sans semicolon) to update the integer scheduling priority
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INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
|
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reduce the priority to execute INSN later. Do not define this macro if
|
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you do not need to adjust the scheduling priorities of insns.
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|
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A STD instruction should be scheduled earlier,
|
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in order to use the bypass. */
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|
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static int
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s390_adjust_priority (insn, priority)
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rtx insn ATTRIBUTE_UNUSED;
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int priority;
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{
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if (! INSN_P (insn))
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return priority;
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if (s390_tune != PROCESSOR_2084_Z990)
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return priority;
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|
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switch (s390_safe_attr_type (insn))
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{
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case TYPE_FSTORED:
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case TYPE_FSTORES:
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priority = priority << 3;
|
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break;
|
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case TYPE_STORE:
|
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priority = priority << 1;
|
||||
break;
|
||||
default:
|
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break;
|
||||
}
|
||||
return priority;
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||||
}
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|
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/* The number of instructions that can be issued per cycle. */
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|
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static int
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s390_issue_rate ()
|
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{
|
||||
if (s390_tune == PROCESSOR_2084_Z990)
|
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return 3;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -3702,12 +3754,34 @@ s390_issue_rate ()
|
|||
static int
|
||||
s390_use_dfa_pipeline_interface ()
|
||||
{
|
||||
if (s390_tune == PROCESSOR_2064_Z900)
|
||||
if (s390_tune == PROCESSOR_2064_Z900
|
||||
|| s390_tune == PROCESSOR_2084_Z990)
|
||||
return 1;
|
||||
return 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
s390_first_cycle_multipass_dfa_lookahead ()
|
||||
{
|
||||
return s390_use_dfa_pipeline_interface () ? 4 : 0;
|
||||
}
|
||||
|
||||
/* Called after issuing each insn.
|
||||
Triggers default sort algorithm to better slot instructions. */
|
||||
|
||||
static int
|
||||
s390_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
|
||||
FILE *dump ATTRIBUTE_UNUSED;
|
||||
int sched_verbose ATTRIBUTE_UNUSED;
|
||||
rtx *ready ATTRIBUTE_UNUSED;
|
||||
int *pn_ready ATTRIBUTE_UNUSED;
|
||||
int clock_var ATTRIBUTE_UNUSED;
|
||||
{
|
||||
return s390_issue_rate();
|
||||
}
|
||||
|
||||
|
||||
/* Split all branches that exceed the maximum distance.
|
||||
Returns true if this created a new literal pool entry.
|
||||
|
||||
|
|
|
|||
|
|
@ -219,6 +219,7 @@
|
|||
;; Pipeline description for z900
|
||||
|
||||
(include "2064.md")
|
||||
(include "2084.md")
|
||||
|
||||
;; Length in bytes.
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue