diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc
index 7c28743f2ee..07753297c38 100644
--- a/gcc/config/alpha/alpha.cc
+++ b/gcc/config/alpha/alpha.cc
@@ -3625,10 +3625,6 @@ alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
   rtx sreg, areg, tmp, smema;
   HOST_WIDE_INT i;
 
-  smema = XEXP (smem, 0);
-  if (GET_CODE (smema) == LO_SUM)
-    smema = force_reg (Pmode, smema);
-
   /* Generate all the tmp registers we need.  */
   for (i = 0; i < words; ++i)
     {
@@ -3640,6 +3636,10 @@ alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
   if (ofs != 0)
     smem = adjust_address (smem, GET_MODE (smem), ofs);
 
+  smema = XEXP (smem, 0);
+  if (GET_CODE (smema) == LO_SUM)
+    smema = force_reg (Pmode, smema);
+
   /* Load up all of the source data.  */
   for (i = 0; i < words; ++i)
     {
@@ -3698,10 +3698,6 @@ alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
   rtx st_addr_1, st_addr_2, dmema;
   HOST_WIDE_INT i;
 
-  dmema = XEXP (dmem, 0);
-  if (GET_CODE (dmema) == LO_SUM)
-    dmema = force_reg (Pmode, dmema);
-
   /* Generate all the tmp registers we need.  */
   if (data_regs != NULL)
     for (i = 0; i < words; ++i)
@@ -3712,6 +3708,10 @@ alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
   if (ofs != 0)
     dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
 
+  dmema = XEXP (dmem, 0);
+  if (GET_CODE (dmema) == LO_SUM)
+    dmema = force_reg (Pmode, dmema);
+
   st_addr_2 = change_address (dmem, DImode,
 			      gen_rtx_AND (DImode,
 					   plus_constant (DImode, dmema,
diff --git a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c
new file mode 100644
index 00000000000..06d0f0beffb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-ptr.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-mbwx" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+typedef unsigned int __attribute__ ((mode (QI))) int08_t;
+typedef unsigned int __attribute__ ((mode (HI))) int16_t;
+
+typedef struct
+  {
+    int08_t v[9];
+  }
+s_t;
+
+typedef union
+  {
+    struct
+      {
+	int08_t c[1];
+	s_t s;
+	int08_t d[6];
+      };
+    int16_t a;
+  }
+u_t;
+
+void __attribute__ ((noinline))
+memclr_a2_o1_c9 (u_t *u)
+{
+  u->s = (s_t) { 0 };
+}
+
+/* Expect assembly such as:
+
+	ldq_u $2,9($16)
+	stb $31,1($16)
+	lda $3,2($16)
+	ldq_u $1,2($16)
+	mskqh $2,$3,$2
+	stq_u $2,9($16)
+	mskql $1,$3,$1
+	stq_u $1,2($16)
+
+   that is with a byte store at offset 1 and with two unaligned load/store
+   pairs at offsets 2 and 9 each.  */
+
+/* { dg-final { scan-assembler-times "\\sldq_u\\s\\\$\[0-9\]+,2\\\(\\\$16\\\)\\s" 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times "\\sldq_u\\s\\\$\[0-9\]+,9\\\(\\\$16\\\)\\s" 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times "\\sstb\\s\\\$31,1\\\(\\\$16\\\)\\s" 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times "\\sstq_u\\s\\\$\[0-9\]+,2\\\(\\\$16\\\)\\s" 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times "\\sstq_u\\s\\\$\[0-9\]+,9\\\(\\\$16\\\)\\s" 1 { xfail *-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-run.c b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-run.c
new file mode 100644
index 00000000000..43ba14701d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/alpha/memclr-a2-o1-c9-run.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "" } */
+
+#include "memclr-a2-o1-c9-ptr.c"
+
+u_t u = { { { [0] = 0xaa }, {{ [0 ... 8] = 0xaa }}, { [0 ... 5] = 0xaa } } };
+
+int
+main (void)
+{
+  int i;
+
+  memclr_a2_o1_c9 (&u);
+  asm ("" : : : "memory");
+  for (i = 0; i < sizeof (u.c); i++)
+    if (u.c[i] != 0xaa)
+      __builtin_abort ();
+  for (i = 0; i < sizeof (u.s.v); i++)
+    if (u.s.v[i] != 0x00)
+      __builtin_abort ();
+  for (i = 0; i < sizeof (u.d); i++)
+    if (u.d[i] != 0xaa)
+      __builtin_abort ();
+  return 0;
+}