S/390: Add missing comments listing mnemonics.
These were useful in the past but are currently lacking on a couple of patterns. Fixed with this patch. gcc/ChangeLog: 2017-02-02 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/s390.md: Add missing comments with the expanded mnemonics. * config/s390/vector.md: Likewise. * config/s390/vx-builtins.md: Likewise. From-SVN: r245122
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Andreas Krebbel
Andreas Krebbel
parent
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4 changed files with 41 additions and 0 deletions
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@ -1,3 +1,10 @@
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2017-02-02 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* config/s390/s390.md: Add missing comments with the expanded
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mnemonics.
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* config/s390/vector.md: Likewise.
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* config/s390/vx-builtins.md: Likewise.
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2017-02-02 Jakub Jelinek <jakub@redhat.com>
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PR target/79197
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@ -4095,6 +4095,7 @@
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operands[6] = operands[0];
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})
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; rosbg, rxsbg
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(define_insn "*r<noxa>sbg_<mode>_noshift"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
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(IXOR:GPR
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@ -4106,6 +4107,7 @@
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"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
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[(set_attr "op_type" "RIE")])
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; rosbg, rxsbg
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(define_insn "*r<noxa>sbg_di_rotl"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
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(IXOR:DI
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@ -4120,6 +4122,7 @@
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"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
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[(set_attr "op_type" "RIE")])
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; rosbg, rxsbg
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(define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
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(IXOR:GPR
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@ -4136,6 +4139,7 @@
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"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
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[(set_attr "op_type" "RIE")])
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; rosbg, rxsbg
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(define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
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(IXOR:GPR
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@ -4155,6 +4159,7 @@
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;; unsigned {int,long} a, b
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;; a = a | (b << const_int)
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;; a = a ^ (b << const_int)
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; rosbg, rxsbg
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(define_insn "*r<noxa>sbg_<mode>_sll"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
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(IXOR:GPR
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@ -4170,6 +4175,7 @@
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;; unsigned {int,long} a, b
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;; a = a | (b >> const_int)
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;; a = a ^ (b >> const_int)
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; rosbg, rxsbg
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(define_insn "*r<noxa>sbg_<mode>_srl"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
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(IXOR:GPR
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@ -10671,6 +10677,7 @@
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; FIXME: There is also mvcin but we cannot use it since src and target
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; may overlap.
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; lrvr, lrv, strv, lrvgr, lrvg, strvg
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(define_insn "bswap<mode>2"
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[(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
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(bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
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@ -144,6 +144,7 @@
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(include "vx-builtins.md")
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; Full HW vector size moves
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; vgmb, vgmh, vgmf, vgmg, vrepib, vrepih, vrepif, vrepig
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(define_insn "mov<mode>"
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[(set (match_operand:V_128 0 "nonimmediate_operand" "=v,v,R, v, v, v, v, v,v,d")
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(match_operand:V_128 1 "general_operand" " v,R,v,j00,jm1,jyy,jxx,jKK,d,v"))]
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@ -329,6 +330,7 @@
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; FIXME: A target memory operand seems to be useful otherwise we end
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; up with vl vlvgg vst. Shouldn't the middle-end be able to handle
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; that itself?
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; vlvgb, vlvgh, vlvgf, vlvgg, vleb, vleh, vlef, vleg, vleib, vleih, vleif, vleig
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(define_insn "*vec_set<mode>"
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[(set (match_operand:V 0 "register_operand" "=v,v,v")
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(unspec:V [(match_operand:<non_vec> 1 "general_operand" "d,R,K")
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@ -344,6 +346,7 @@
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vlei<bhfgq>\t%v0,%1,%2"
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[(set_attr "op_type" "VRS,VRX,VRI")])
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; vlvgb, vlvgh, vlvgf, vlvgg
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(define_insn "*vec_set<mode>_plus"
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[(set (match_operand:V 0 "register_operand" "=v")
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(unspec:V [(match_operand:<non_vec> 1 "general_operand" "d")
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@ -366,6 +369,7 @@
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UNSPEC_VEC_EXTRACT))]
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"TARGET_VX")
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; vlgvb, vlgvh, vlgvf, vlgvg, vsteb, vsteh, vstef, vsteg
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(define_insn "*vec_extract<mode>"
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[(set (match_operand:<non_vec> 0 "nonimmediate_operand" "=d,R")
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(unspec:<non_vec> [(match_operand:V 1 "register_operand" "v,v")
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@ -379,6 +383,7 @@
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vste<bhfgq>\t%v1,%0,%2"
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[(set_attr "op_type" "VRS,VRX")])
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; vlgvb, vlgvh, vlgvf, vlgvg
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(define_insn "*vec_extract<mode>_plus"
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[(set (match_operand:<non_vec> 0 "nonimmediate_operand" "=d")
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(unspec:<non_vec> [(match_operand:V 1 "register_operand" "v")
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@ -399,6 +404,7 @@
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})
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; Replicate from vector element
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; vrepb, vreph, vrepf, vrepg
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(define_insn "*vec_splat<mode>"
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[(set (match_operand:V_HW 0 "register_operand" "=v")
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(vec_duplicate:V_HW
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@ -410,6 +416,7 @@
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"vrep<bhfgq>\t%v0,%v1,%2"
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[(set_attr "op_type" "VRI")])
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; vlrepb, vlreph, vlrepf, vlrepg, vrepib, vrepih, vrepif, vrepig, vrepb, vreph, vrepf, vrepg
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(define_insn "*vec_splats<mode>"
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[(set (match_operand:V_HW 0 "register_operand" "=v,v,v,v")
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(vec_duplicate:V_HW (match_operand:<non_vec> 1 "general_operand" " R,K,v,d")))]
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@ -692,6 +699,7 @@
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})
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; Count leading zeros
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; vclzb, vclzh, vclzf, vclzg
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(define_insn "clz<mode>2"
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[(set (match_operand:V 0 "register_operand" "=v")
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(clz:V (match_operand:V 1 "register_operand" "v")))]
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@ -700,6 +708,7 @@
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[(set_attr "op_type" "VRR")])
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; Count trailing zeros
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; vctzb, vctzh, vctzf, vctzg
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(define_insn "ctz<mode>2"
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[(set (match_operand:V 0 "register_operand" "=v")
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(ctz:V (match_operand:V 1 "register_operand" "v")))]
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@ -65,6 +65,7 @@
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; Vector gather element
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; vgef, vgeg
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(define_insn "vec_gather_element<mode>"
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[(set (match_operand:V_HW_32_64 0 "register_operand" "=v")
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(unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0")
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@ -167,6 +168,7 @@
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; vec_extract is also an RTL standard name -> vector.md
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; vllezb, vllezh, vllezf, vllezg
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(define_insn "vec_insert_and_zero<mode>"
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[(set (match_operand:V_HW 0 "register_operand" "=v")
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(unspec:V_HW [(match_operand:<non_vec> 1 "memory_operand" "R")]
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@ -187,6 +189,7 @@
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; FIXME: The following two patterns might using vec_merge. But what is
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; the canonical form: (vec_select (vec_merge op0 op1)) or (vec_merge
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; (vec_select op0) (vec_select op1)
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; vmrhb, vmrhh, vmrhf, vmrhg
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(define_insn "vec_mergeh<mode>"
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[(set (match_operand:V_HW 0 "register_operand" "=v")
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(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
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@ -196,6 +199,7 @@
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"vmrh<bhfgq>\t%v0,%1,%2"
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[(set_attr "op_type" "VRR")])
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; vmrlb, vmrlh, vmrlf, vmrlg
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(define_insn "vec_mergel<mode>"
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[(set (match_operand:V_HW 0 "register_operand" "=v")
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(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
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@ -208,6 +212,7 @@
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; Vector pack
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; vpkh, vpkf, vpkg
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(define_insn "vec_pack<mode>"
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[(set (match_operand:<vec_half> 0 "register_operand" "=v")
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(unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
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@ -220,6 +225,7 @@
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; Vector pack saturate
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; vpksh, vpksf, vpksg
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(define_insn "vec_packs<mode>"
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[(set (match_operand:<vec_half> 0 "register_operand" "=v")
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(unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
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@ -249,6 +255,7 @@
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operands[4] = gen_reg_rtx (SImode);
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})
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; vpksh, vpksf, vpksg
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(define_insn "*vec_packs_cc<mode>"
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[(set (reg:CCRAW CC_REGNUM)
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(unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v")
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@ -264,6 +271,7 @@
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; Vector pack logical saturate
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; vpklsh, vpklsf, vpklsg
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(define_insn "vec_packsu<mode>"
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[(set (match_operand:<vec_half> 0 "register_operand" "=v")
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(unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand" "v")
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@ -322,6 +330,7 @@
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operands[4] = gen_reg_rtx (SImode);
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})
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; vpklsh, vpklsf, vpklsg
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(define_insn "*vec_packsu_cc<mode>"
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[(set (reg:CCRAW CC_REGNUM)
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(unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v")
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[(set_attr "op_type" "VRV")])
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; A 31 bit target address is generated from 64 bit elements
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; vsceg
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(define_insn "vec_scatter_element<V_HW_64:mode>_SI"
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[(set (mem:<non_vec>
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(plus:SI (subreg:SI
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@ -417,6 +427,7 @@
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[(set_attr "op_type" "VRV")])
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; Element size and target address size is the same
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; vscef, vsceg
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(define_insn "vec_scatter_element<mode>_<non_vec_int>"
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[(set (mem:<non_vec>
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(plus:<non_vec_int> (unspec:<non_vec_int>
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@ -482,6 +493,7 @@
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; Vector sign extend to doubleword
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; Sign extend of right most vector element to respective double-word
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; vsegb, vsegh, vsegf
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(define_insn "vec_extend<mode>"
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[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
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(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
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@ -551,6 +563,7 @@
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; Vector add compute carry
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; vaccb, vacch, vaccf, vaccg, vaccq
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(define_insn "vacc<bhfgq>_<mode>"
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[(set (match_operand:VIT_HW 0 "register_operand" "=v")
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(unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "%v")
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@ -638,6 +651,7 @@
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; Vector average
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; vavgb, vavgh, vavgf, vavgg
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(define_insn "vec_avg<mode>"
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[(set (match_operand:VI_HW 0 "register_operand" "=v")
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(unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
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@ -649,6 +663,7 @@
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; Vector average logical
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; vavglb, vavglh, vavglf, vavglg
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(define_insn "vec_avgu<mode>"
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[(set (match_operand:VI_HW 0 "register_operand" "=v")
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(unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
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@ -787,6 +802,7 @@
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; Vector Galois field multiply sum
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; vgfmb, vgfmh, vgfmf
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(define_insn "vec_gfmsum<mode>"
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[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
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(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
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@ -805,6 +821,7 @@
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"vgfmg\t%v0,%v1,%v2"
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[(set_attr "op_type" "VRR")])
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; vgfmab, vgfmah, vgfmaf
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(define_insn "vec_gfmsum_accum<mode>"
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[(set (match_operand:<vec_double> 0 "register_operand" "=v")
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(unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
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@ -1115,6 +1132,7 @@
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; Vector subtract compute borrow indication
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; vscbib, vscbih, vscbif, vscbig, vscbiq
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(define_insn "vscbi<bhfgq>_<mode>"
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[(set (match_operand:VIT_HW 0 "register_operand" "=v")
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(unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "v")
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