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re PR target/45336 (pextr{b,w,d}, (worse than) redundant extensions)

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PR target/45336
	* config/i386/sse.md (*sse4_1_pextrb): Add SWI48 mode iterator
	to cover zero extension into 64-bit register.
	(*sse2_pextrw): Likewise.
	(*sse4_1_pextrd_zext): New insn.

From-SVN: r163420
This commit is contained in:
Jakub Jelinek 2010-08-20 22:54:25 +02:00 • committed by Jakub Jelinek
parent c6d8116af9
commit 50d724a750
2 changed files with 30 additions and 8 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2010-08-20 Jakub Jelinek <jakub@redhat.com>
PR target/45336
* config/i386/sse.md (*sse4_1_pextrb): Add SWI48 mode iterator
to cover zero extension into 64-bit register.
(*sse2_pextrw): Likewise.
(*sse4_1_pextrd_zext): New insn.
2010-08-20 Iain Sandoe <iains@gcc.gnu.org>
revert r163410, partially revert r163267.

30
gcc/config/i386/sse.md
View file

@ -7075,14 +7075,14 @@
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_pextrb"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI
(define_insn "*sse4_1_pextrb_<mode>"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(zero_extend:SWI48
(vec_select:QI
(match_operand:V16QI 1 "register_operand" "x")
(parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")]))))]
"TARGET_SSE4_1"
"%vpextrb\t{%2, %1, %0|%0, %1, %2}"
"%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
@ -7102,14 +7102,14 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse2_pextrw"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI
(define_insn "*sse2_pextrw_<mode>"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(zero_extend:SWI48
(vec_select:HI
(match_operand:V8HI 1 "register_operand" "x")
(parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))]
"TARGET_SSE2"
"%vpextrw\t{%2, %1, %0|%0, %1, %2}"
"%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "length_immediate" "1")
@ -7142,6 +7142,20 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_pextrd_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(vec_select:SI
(match_operand:V4SI 1 "register_operand" "x")
(parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
"TARGET_64BIT && TARGET_SSE4_1"
"%vpextrd\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
;; It must come before *vec_extractv2di_1_sse since it is preferred.
(define_insn "*sse4_1_pextrq"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")