Fix bswap patterns for trunk.
Committed by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 2010-01-28 Stephen Thomas <stephen.thomas@arm.com> * config/arm/arm.md (bswapsi2): Add support for bswapsi2. (arm_rev): New. (arm_legacy_rev): Likewise. (thumb_legacy_rev): Likewise. 2010-01-28 Stephen Thomas <stephen.thomas@arm.com> * testsuite/gcc.dg/optimize-bswap*.c: Add ARM target From-SVN: r156313
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5 changed files with 114 additions and 2 deletions
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@ -1,3 +1,10 @@
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2010-01-28 Stephen Thomas <stephen.thomas@arm.com>
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* config/arm/arm.md (bswapsi2): Add support for bswapsi2.
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(arm_rev): New.
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(arm_legacy_rev): Likewise.
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(thumb_legacy_rev): Likewise.
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2010-01-27 Jakub Jelinek <jakub@redhat.com>
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* dwarf2out.c (mem_loc_descriptor): Remove special casing of
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@ -11194,6 +11194,107 @@
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(set_attr "length" "4")]
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)
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(define_insn "arm_rev"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
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"TARGET_EITHER && arm_arch6"
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"rev\t%0, %1"
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[(set (attr "length")
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(if_then_else (eq_attr "is_thumb" "yes")
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(const_int 2)
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(const_int 4)))]
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)
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(define_expand "arm_legacy_rev"
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[(set (match_operand:SI 2 "s_register_operand" "")
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(xor:SI (rotatert:SI (match_operand:SI 1 "s_register_operand" "")
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(const_int 16))
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(match_dup 1)))
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(set (match_dup 2)
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(lshiftrt:SI (match_dup 2)
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(const_int 8)))
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(set (match_operand:SI 3 "s_register_operand" "")
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(rotatert:SI (match_dup 1)
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(const_int 8)))
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(set (match_dup 2)
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(and:SI (match_dup 2)
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(const_int -65281)))
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(set (match_operand:SI 0 "s_register_operand" "")
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(xor:SI (match_dup 3)
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(match_dup 2)))]
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"TARGET_32BIT"
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""
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)
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;; Reuse temporaries to keep register pressure down.
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(define_expand "thumb_legacy_rev"
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[(set (match_operand:SI 2 "s_register_operand" "")
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(ashift:SI (match_operand:SI 1 "s_register_operand" "")
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(const_int 24)))
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(set (match_operand:SI 3 "s_register_operand" "")
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(lshiftrt:SI (match_dup 1)
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(const_int 24)))
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(set (match_dup 3)
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(ior:SI (match_dup 3)
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(match_dup 2)))
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(set (match_operand:SI 4 "s_register_operand" "")
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(const_int 16))
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(set (match_operand:SI 5 "s_register_operand" "")
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(rotatert:SI (match_dup 1)
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(match_dup 4)))
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(set (match_dup 2)
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(ashift:SI (match_dup 5)
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(const_int 24)))
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(set (match_dup 5)
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(lshiftrt:SI (match_dup 5)
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(const_int 24)))
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(set (match_dup 5)
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(ior:SI (match_dup 5)
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(match_dup 2)))
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(set (match_dup 5)
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(rotatert:SI (match_dup 5)
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(match_dup 4)))
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(set (match_operand:SI 0 "s_register_operand" "")
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(ior:SI (match_dup 5)
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(match_dup 3)))]
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"TARGET_THUMB"
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""
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)
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(define_expand "bswapsi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
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"TARGET_EITHER"
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"
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if (!arm_arch6)
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{
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if (!optimize_size)
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{
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rtx op2 = gen_reg_rtx (SImode);
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rtx op3 = gen_reg_rtx (SImode);
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if (TARGET_THUMB)
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{
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rtx op4 = gen_reg_rtx (SImode);
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rtx op5 = gen_reg_rtx (SImode);
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emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
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op2, op3, op4, op5));
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}
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else
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{
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emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
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op2, op3));
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}
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DONE;
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}
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else
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FAIL;
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}
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"
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)
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;; Load the FPA co-processor patterns
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(include "fpa.md")
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;; Load the Maverick co-processor patterns
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@ -1,3 +1,7 @@
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2010-01-27 Stephen Thomas <stephen.thomas@arm.com>
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* testsuite/gcc.dg/optimize-bswap*.c: Add ARM target
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2010-01-27 Richard Guenther <rguenther@suse.de>
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PR middle-end/42878
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@ -1,4 +1,4 @@
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/* { dg-do compile { target alpha*-*-* ia64*-*-* x86_64-*-* s390x-*-* powerpc*-*-* rs6000-*-* } } */
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/* { dg-do compile { target arm*-*-* alpha*-*-* ia64*-*-* x86_64-*-* s390x-*-* powerpc*-*-* rs6000-*-* } } */
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/* { dg-require-effective-target stdint_types } */
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/* { dg-require-effective-target lp64 } */
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/* { dg-options "-O2 -fdump-tree-bswap" } */
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@ -1,4 +1,4 @@
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/* { dg-do compile { target alpha*-*-* i?86-*-* powerpc*-*-* rs6000-*-* x86_64-*-* s390*-*-* } } */
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/* { dg-do compile { target arm*-*-* alpha*-*-* i?86-*-* powerpc*-*-* rs6000-*-* x86_64-*-* s390*-*-* } } */
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/* { dg-require-effective-target stdint_types } */
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/* { dg-options "-O2 -fdump-tree-bswap" } */
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