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sse.md (*avx_cvtdq2pd256_2): Rename to...

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* config/i386/sse.md (*avx_cvtdq2pd256_2): Rename to...
	(avx_cvtdq2pd256_2): ... this.
	(sseunpackfltmode): New mode attr.
	(vec_unpacks_float_hi_v8hi, vec_unpacks_float_lo_v8hi,
	vec_unpacku_float_hi_v8hi, vec_unpacku_float_lo_v8hi): Macroize
	using VI2_AVX2 iterator.
	(vec_unpacku_float_hi_v8si, vec_unpacku_float_lo_v8si): New
	expanders.

From-SVN: r179960
This commit is contained in:
Jakub Jelinek 2011-10-14 08:06:14 +02:00 • committed by Jakub Jelinek
parent 8e24e4091c
commit 4fbe3b8a2b
2 changed files with 95 additions and 25 deletions
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11
gcc/ChangeLog
View file

@ -1,3 +1,14 @@
2011-10-14 Jakub Jelinek <jakub@redhat.com>
* config/i386/sse.md (*avx_cvtdq2pd256_2): Rename to...
(avx_cvtdq2pd256_2): ... this.
(sseunpackfltmode): New mode attr.
(vec_unpacks_float_hi_v8hi, vec_unpacks_float_lo_v8hi,
vec_unpacku_float_hi_v8hi, vec_unpacku_float_lo_v8hi): Macroize
using VI2_AVX2 iterator.
(vec_unpacku_float_hi_v8si, vec_unpacku_float_lo_v8si): New
expanders.
2011-10-13 David S. Miller <davem@davemloft.net>
* config/sparc/sparc.md (plusminus): New code iterator.

109
gcc/config/i386/sse.md
View file

@ -2517,7 +2517,7 @@
(set_attr "prefix" "vex")
(set_attr "mode" "V4DF")])
(define_insn "*avx_cvtdq2pd256_2"
(define_insn "avx_cvtdq2pd256_2"
[(set (match_operand:V4DF 0 "register_operand" "=x")
(float:V4DF
(vec_select:V4SI
@ -2786,51 +2786,58 @@
(const_int 2) (const_int 3)]))))]
"TARGET_AVX")
(define_expand "vec_unpacks_float_hi_v8hi"
[(match_operand:V4SF 0 "register_operand" "")
(match_operand:V8HI 1 "register_operand" "")]
(define_mode_attr sseunpackfltmode
[(V8HI "V4SF") (V4SI "V2DF") (V16HI "V8SF") (V8SI "V4DF")])
(define_expand "vec_unpacks_float_hi_<mode>"
[(match_operand:<sseunpackfltmode> 0 "register_operand" "")
(match_operand:VI2_AVX2 1 "register_operand" "")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (V4SImode);
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
emit_insn (gen_vec_unpacks_hi_<mode> (tmp, operands[1]));
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_FLOAT (<sseunpackfltmode>mode, tmp)));
DONE;
})
(define_expand "vec_unpacks_float_lo_v8hi"
[(match_operand:V4SF 0 "register_operand" "")
(match_operand:V8HI 1 "register_operand" "")]
(define_expand "vec_unpacks_float_lo_<mode>"
[(match_operand:<sseunpackfltmode> 0 "register_operand" "")
(match_operand:VI2_AVX2 1 "register_operand" "")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (V4SImode);
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
emit_insn (gen_vec_unpacks_lo_<mode> (tmp, operands[1]));
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_FLOAT (<sseunpackfltmode>mode, tmp)));
DONE;
})
(define_expand "vec_unpacku_float_hi_v8hi"
[(match_operand:V4SF 0 "register_operand" "")
(match_operand:V8HI 1 "register_operand" "")]
(define_expand "vec_unpacku_float_hi_<mode>"
[(match_operand:<sseunpackfltmode> 0 "register_operand" "")
(match_operand:VI2_AVX2 1 "register_operand" "")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (V4SImode);
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
emit_insn (gen_vec_unpacku_hi_<mode> (tmp, operands[1]));
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_FLOAT (<sseunpackfltmode>mode, tmp)));
DONE;
})
(define_expand "vec_unpacku_float_lo_v8hi"
[(match_operand:V4SF 0 "register_operand" "")
(match_operand:V8HI 1 "register_operand" "")]
(define_expand "vec_unpacku_float_lo_<mode>"
[(match_operand:<sseunpackfltmode> 0 "register_operand" "")
(match_operand:VI2_AVX2 1 "register_operand" "")]
"TARGET_SSE2"
{
rtx tmp = gen_reg_rtx (V4SImode);
rtx tmp = gen_reg_rtx (<sseunpackmode>mode);
emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
emit_insn (gen_vec_unpacku_lo_<mode> (tmp, operands[1]));
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_FLOAT (<sseunpackfltmode>mode, tmp)));
DONE;
})
@ -2942,6 +2949,58 @@
operands[i] = gen_reg_rtx (V2DFmode);
})
(define_expand "vec_unpacku_float_hi_v8si"
[(match_operand:V4DF 0 "register_operand" "")
(match_operand:V8SI 1 "register_operand" "")]
"TARGET_AVX"
{
REAL_VALUE_TYPE TWO32r;
rtx x, tmp[6];
int i;
real_ldexp (&TWO32r, &dconst1, 32);
x = const_double_from_real_value (TWO32r, DFmode);
tmp[0] = force_reg (V4DFmode, CONST0_RTX (V4DFmode));
tmp[1] = force_reg (V4DFmode, ix86_build_const_vector (V4DFmode, 1, x));
tmp[5] = gen_reg_rtx (V4SImode);
for (i = 2; i < 5; i++)
tmp[i] = gen_reg_rtx (V4DFmode);
emit_insn (gen_vec_extract_hi_v8si (tmp[5], operands[1]));
emit_insn (gen_avx_cvtdq2pd256 (tmp[2], tmp[5]));
emit_insn (gen_rtx_SET (VOIDmode, tmp[3],
gen_rtx_LT (V4DFmode, tmp[2], tmp[0])));
emit_insn (gen_andv4df3 (tmp[4], tmp[3], tmp[1]));
emit_insn (gen_addv4df3 (operands[0], tmp[2], tmp[4]));
DONE;
})
(define_expand "vec_unpacku_float_lo_v8si"
[(match_operand:V4DF 0 "register_operand" "")
(match_operand:V8SI 1 "nonimmediate_operand" "")]
"TARGET_AVX"
{
REAL_VALUE_TYPE TWO32r;
rtx x, tmp[5];
int i;
real_ldexp (&TWO32r, &dconst1, 32);
x = const_double_from_real_value (TWO32r, DFmode);
tmp[0] = force_reg (V4DFmode, CONST0_RTX (V4DFmode));
tmp[1] = force_reg (V4DFmode, ix86_build_const_vector (V4DFmode, 1, x));
for (i = 2; i < 5; i++)
tmp[i] = gen_reg_rtx (V4DFmode);
emit_insn (gen_avx_cvtdq2pd256_2 (tmp[2], operands[1]));
emit_insn (gen_rtx_SET (VOIDmode, tmp[3],
gen_rtx_LT (V4DFmode, tmp[2], tmp[0])));
emit_insn (gen_andv4df3 (tmp[4], tmp[3], tmp[1]));
emit_insn (gen_addv4df3 (operands[0], tmp[2], tmp[4]));
DONE;
})
(define_expand "vec_pack_trunc_v4df"
[(set (match_dup 3)
(float_truncate:V4SF