Fix minor bugs in H8 port logical ops. Prepare for more compare/test removal
gcc/ * config/h8300/h8300-protos.h (compute_a_shift_length): Drop unused argument from prototype. (output_logical_op): Add rtx_code argument. (compute_logical_op_length): Likewise. * config/h8300/h8300.c (h8300_and_costs): Pass additional argument to compute_a_shift_length. (output_logical_op); New argument with the rtx code rather than extracting it from an operand. Handle QImode too. (compute_logical_op_length): Similary. (compute_a_shift_length): Drop unused argument. * config/h8300/h8300.md (logicals): New code iterator. * config/h8300/logical.md (<code><mode>3 expander): Combine the "and" expander with the "ior"/"xor" expander. (bclr<mode>msx): Combine the QI/HI mode patterns. (<logical><mode>3 insns): Use code iterator rather than match_operator. Handle QImode as well. Update call to output_logical_op and compute_logical_op_length to pass in rtx_code Fix split condition on all define_insn_and_split patterns. (one_cmpl<mode>2<cczn>): Use <cczn> to support both clobbering the flags and setting ZN via existing define_subst. * config/h8300/shiftrotate.md: Drop unused argument from calls to compute_a_shift_length. Signed-off-by: Jeff Law <jeffreyalaw@gmail.com>
This commit is contained in:
Jeff Law
parent
b75978d14f
commit
4ea5fe8b40
5 changed files with 55 additions and 64 deletions
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@ -29,16 +29,15 @@ extern unsigned int compute_mov_length (rtx *);
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extern const char *output_plussi (rtx *, bool);
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extern unsigned int compute_plussi_length (rtx *, bool);
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extern const char *output_a_shift (rtx *);
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extern unsigned int compute_a_shift_length (rtx, rtx *);
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extern unsigned int compute_a_shift_length (rtx *);
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extern const char *output_a_rotate (enum rtx_code, rtx *);
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extern unsigned int compute_a_rotate_length (rtx *);
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extern const char *output_simode_bld (int, rtx[]);
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extern void final_prescan_insn (rtx_insn *, rtx *, int);
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extern int h8300_expand_movsi (rtx[]);
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extern machine_mode h8300_select_cc_mode (RTX_CODE, rtx, rtx);
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extern const char *output_logical_op (machine_mode, rtx *);
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extern unsigned int compute_logical_op_length (machine_mode,
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rtx *);
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extern const char *output_logical_op (machine_mode, rtx_code code, rtx *);
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extern unsigned int compute_logical_op_length (machine_mode, rtx_code, rtx *);
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extern int compute_logical_op_cc (machine_mode, rtx *);
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extern int compute_a_shift_cc (rtx, rtx *);
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@ -1100,7 +1100,7 @@ h8300_and_costs (rtx x)
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operands[1] = XEXP (x, 0);
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operands[2] = XEXP (x, 1);
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operands[3] = x;
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return compute_logical_op_length (GET_MODE (x), operands) / 2;
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return compute_logical_op_length (GET_MODE (x), AND, operands) / 2;
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}
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/* Compute the cost of a shift insn. */
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@ -1119,7 +1119,7 @@ h8300_shift_costs (rtx x)
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operands[1] = NULL;
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operands[2] = XEXP (x, 1);
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operands[3] = x;
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return compute_a_shift_length (NULL, operands) / 2;
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return compute_a_shift_length (operands) / 2;
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}
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/* Worker function for TARGET_RTX_COSTS. */
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@ -2879,10 +2879,8 @@ compute_plussi_cc (rtx *operands)
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/* Output a logical insn. */
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const char *
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output_logical_op (machine_mode mode, rtx *operands)
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output_logical_op (machine_mode mode, rtx_code code, rtx *operands)
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{
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/* Figure out the logical op that we need to perform. */
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enum rtx_code code = GET_CODE (operands[3]);
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/* Pretend that every byte is affected if both operands are registers. */
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const unsigned HOST_WIDE_INT intval =
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(unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
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@ -2923,6 +2921,10 @@ output_logical_op (machine_mode mode, rtx *operands)
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switch (mode)
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{
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case E_QImode:
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sprintf (insn_buf, "%s.b\t%%X2,%%X0", opname);
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output_asm_insn (insn_buf, operands);
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break;
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case E_HImode:
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/* First, see if we can finish with one insn. */
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if (b0 != 0 && b1 != 0)
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@ -3033,10 +3035,8 @@ output_logical_op (machine_mode mode, rtx *operands)
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/* Compute the length of a logical insn. */
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unsigned int
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compute_logical_op_length (machine_mode mode, rtx *operands)
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compute_logical_op_length (machine_mode mode, rtx_code code, rtx *operands)
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{
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/* Figure out the logical op that we need to perform. */
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enum rtx_code code = GET_CODE (operands[3]);
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/* Pretend that every byte is affected if both operands are registers. */
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const unsigned HOST_WIDE_INT intval =
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(unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
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@ -3061,6 +3061,9 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
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switch (mode)
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{
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case E_QImode:
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return 2;
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case E_HImode:
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/* First, see if we can finish with one insn. */
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if (b0 != 0 && b1 != 0)
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@ -4189,7 +4192,7 @@ h8300_asm_insn_count (const char *templ)
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/* Compute the length of a shift insn. */
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unsigned int
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compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
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compute_a_shift_length (rtx *operands)
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{
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rtx shift = operands[3];
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machine_mode mode = GET_MODE (shift);
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@ -229,6 +229,8 @@
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(define_code_iterator shifts [ashift ashiftrt lshiftrt])
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(define_code_iterator logicals [ior xor and])
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(define_code_iterator ors [ior xor])
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(include "movepush.md")
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@ -1,11 +1,20 @@
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;; Generic for binary logicals across the supported integer modes
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(define_expand "<code><mode>3"
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[(set (match_operand:QHSI 0 "register_operand" "")
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(logicals:QHSI (match_operand:QHSI 1 "register_operand" "")
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(match_operand:QHSI 2 "h8300_src_operand" "")))]
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""
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"")
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;; There's a ton of cleanup to do from here below.
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;; ----------------------------------------------------------------------
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;; AND INSTRUCTIONS
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;; ----------------------------------------------------------------------
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(define_insn "bclrqi_msx"
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[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
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(and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
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(match_operand:QI 2 "single_zero_operand" "Y0")))]
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(define_insn "bclr<mode>_msx"
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[(set (match_operand:QHI 0 "bit_register_indirect_operand" "=WU")
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(and:QHI (match_operand:QHI 1 "bit_register_indirect_operand" "%0")
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(match_operand:QHI 2 "single_zero_operand" "Y0")))]
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"TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
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"bclr\\t%W2,%0"
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[(set_attr "length" "8")])
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@ -24,21 +33,13 @@
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operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
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})
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(define_insn "bclrhi_msx"
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[(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
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(and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
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(match_operand:HI 2 "single_zero_operand" "Y0")))]
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"TARGET_H8300SX"
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"bclr\\t%W2,%0"
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[(set_attr "length" "8")])
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(define_insn_and_split "*andqi3_2"
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[(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
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(and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
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(match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
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"TARGET_H8300SX"
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"#"
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"reload_completed"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (and:QI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC CC_REG))])])
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@ -62,7 +63,7 @@
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"register_operand (operands[0], QImode)
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|| single_zero_operand (operands[2], QImode)"
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"#"
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"reload_completed"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (and:QI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC CC_REG))])])
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@ -78,13 +79,6 @@
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and %X2,%X0"
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[(set_attr "length" "2,8")])
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(define_expand "and<mode>3"
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[(set (match_operand:QHSI 0 "register_operand" "")
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(and:QHSI (match_operand:QHSI 1 "register_operand" "")
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(match_operand:QHSI 2 "h8300_src_operand" "")))]
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""
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"")
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(define_insn_and_split "*andor<mode>3"
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[(set (match_operand:QHSI 0 "register_operand" "=r")
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(ior:QHSI (and:QHSI (match_operand:QHSI 2 "register_operand" "r")
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@ -95,7 +89,7 @@
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|| (<MODE>mode == SImode
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&& (INTVAL (operands[3]) & 0xffff) != 0))"
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"#"
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"reload_completed"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (ior:QHSI (and:QHSI (match_dup 2)
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(match_dup 3))
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(match_dup 1)))
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@ -150,7 +144,7 @@
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(match_operand:SI 1 "register_operand" "0")))]
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""
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"#"
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"reload_completed"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (ior:SI (and:SI (ashift:SI (match_dup 2)
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(const_int 8))
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(const_int 65280))
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@ -195,7 +189,7 @@
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"TARGET_H8300SX || register_operand (operands[0], QImode)
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|| single_one_operand (operands[2], QImode)"
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"#"
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"reload_completed"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (ors:QI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC CC_REG))])])
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@ -216,39 +210,32 @@
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[(set_attr "length" "8,*")
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(set_attr "length_table" "*,logicb")])
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(define_expand "<code><mode>3"
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[(set (match_operand:QHSI 0 "register_operand" "")
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(ors:QHSI (match_operand:QHSI 1 "register_operand" "")
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(match_operand:QHSI 2 "h8300_src_operand" "")))]
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""
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"")
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;; ----------------------------------------------------------------------
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;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
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;; ----------------------------------------------------------------------
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(define_insn_and_split "*logical<mode>3"
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[(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ")
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(match_operator:HSI 3 "bit_operator"
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[(match_operand:HSI 1 "h8300_dst_operand" "%0")
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(match_operand:HSI 2 "h8300_src_operand" "rQi")]))]
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[(set (match_operand:QHSI 0 "h8300_dst_operand" "=rQ")
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(logicals:QHSI
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(match_operand:QHSI 1 "h8300_dst_operand" "%0")
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(match_operand:QHSI 2 "h8300_src_operand" "rQi")))]
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"h8300_operands_match_p (operands)"
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"#"
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"reload_completed"
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"&& reload_completed"
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[(parallel [(set (match_dup 0)
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(match_op_dup 3 [(match_dup 1) (match_dup 2)]))
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(clobber (reg:CC CC_REG))])])
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(define_insn "*logical<mode>3_clobber_flags"
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[(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ")
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(match_operator:HSI 3 "bit_operator"
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[(match_operand:HSI 1 "h8300_dst_operand" "%0")
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(match_operand:HSI 2 "h8300_src_operand" "rQi")]))
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(define_insn "*<code><mode>3_clobber_flags"
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[(set (match_operand:QHSI 0 "h8300_dst_operand" "=rQ")
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(logicals:QHSI
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(match_operand:QHSI 1 "h8300_dst_operand" "%0")
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(match_operand:QHSI 2 "h8300_src_operand" "rQi")))
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(clobber (reg:CC CC_REG))]
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"h8300_operands_match_p (operands)"
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{ return output_logical_op (<MODE>mode, operands); }
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{ return output_logical_op (<MODE>mode, <CODE>, operands); }
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[(set (attr "length")
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(symbol_ref "compute_logical_op_length (<MODE>mode, operands)"))])
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(symbol_ref "compute_logical_op_length (<MODE>mode, <CODE>, operands)"))])
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;; ----------------------------------------------------------------------
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@ -260,11 +247,11 @@
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(not:QHSI (match_operand:QHSI 1 "h8300_dst_operand" "0")))]
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""
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"#"
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"reload_completed"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (not:QHSI (match_dup 1)))
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(clobber (reg:CC CC_REG))])])
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(define_insn "one_cmpl<mode>2_clobber_flags"
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(define_insn "one_cmpl<mode>2_<cczn>"
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[(set (match_operand:QHSI 0 "h8300_dst_operand" "=rQ")
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(not:QHSI (match_operand:QHSI 1 "h8300_dst_operand" "0")))
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(clobber (reg:CC CC_REG))]
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@ -175,7 +175,7 @@
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return output_a_shift (operands);
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}
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[(set (attr "length")
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(symbol_ref "compute_a_shift_length (insn, operands)"))])
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(symbol_ref "compute_a_shift_length (operands)"))])
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(define_insn_and_split "*shiftqi_noscratch"
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[(set (match_operand:QI 0 "register_operand" "=r,r")
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@ -203,7 +203,7 @@
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return output_a_shift (operands);
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}
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[(set (attr "length")
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(symbol_ref "compute_a_shift_length (insn, operands)"))])
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(symbol_ref "compute_a_shift_length (operands)"))])
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(define_insn_and_split "*shifthi"
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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@ -230,7 +230,7 @@
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return output_a_shift (operands);
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}
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[(set (attr "length")
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(symbol_ref "compute_a_shift_length (insn, operands)"))])
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(symbol_ref "compute_a_shift_length (operands)"))])
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(define_insn_and_split "*shifthi_noscratch"
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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@ -258,7 +258,7 @@
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return output_a_shift (operands);
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}
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[(set (attr "length")
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(symbol_ref "compute_a_shift_length (insn, operands)"))])
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(symbol_ref "compute_a_shift_length (operands)"))])
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(define_insn_and_split "*shiftsi"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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@ -285,7 +285,7 @@
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return output_a_shift (operands);
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}
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[(set (attr "length")
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(symbol_ref "compute_a_shift_length (insn, operands)"))])
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(symbol_ref "compute_a_shift_length (operands)"))])
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(define_insn_and_split "*shiftsi_noscratch"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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@ -313,7 +313,7 @@
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return output_a_shift (operands);
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}
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[(set (attr "length")
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(symbol_ref "compute_a_shift_length (insn, operands)"))])
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(symbol_ref "compute_a_shift_length (operands)"))])
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;; Split a variable shift into a loop. If the register containing
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;; the shift count dies, then we just use that register.
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