procyberian/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

rs6000: support vector int type rotatert

Browse source 
gcc/ChangeLog

2019-08-07  Kewen Lin  <linkw@gcc.gnu.org>

    * config/rs6000/vector.md (vrotr<mode>3): New define_expand.

gcc/testsuite/ChangeLog

2019-08-07  Kewen Lin  <linkw@gcc.gnu.org>

    * gcc.target/powerpc/vec_rotate-1.c: New test.
    * gcc.target/powerpc/vec_rotate-2.c: New test.
    * gcc.target/powerpc/vec_rotate-3.c: New test.
    * gcc.target/powerpc/vec_rotate-4.c: New test.

From-SVN: r274158
This commit is contained in:
Kewen Lin 2019-08-07 07:11:14 +00:00
parent b69e0fabc2
commit 4e708f5ebd
7 changed files with 140 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
gcc/ChangeLog
View file

@ -1,3 +1,7 @@
2019-08-07 Kewen Lin <linkw@gcc.gnu.org>
* config/rs6000/vector.md (vrotr<mode>3): New define_expand.
2019-08-07 Kito Cheng <kito.cheng@sifive.com>
* gcc/config/riscv/multilib-generator: (canonical_order): Add 'g'.

13
gcc/config/rs6000/vector.md
View file

@ -1260,6 +1260,19 @@
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for rotatert to make use of vrotl
(define_expand "vrotr<mode>3"
[(set (match_operand:VEC_I 0 "vint_operand")
(rotatert:VEC_I (match_operand:VEC_I 1 "vint_operand")
(match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rtx rot_count = gen_reg_rtx (<MODE>mode);
emit_insn (gen_neg<mode>2 (rot_count, operands[2]));
emit_insn (gen_vrotl<mode>3 (operands[0], operands[1], rot_count));
DONE;
})
;; Expanders for arithmetic shift left on each vector element
(define_expand "vashl<mode>3"
[(set (match_operand:VEC_I 0 "vint_operand")

7
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,10 @@
2019-08-07 Kewen Lin <linkw@gcc.gnu.org>
* gcc.target/powerpc/vec_rotate-1.c: New test.
* gcc.target/powerpc/vec_rotate-2.c: New test.
* gcc.target/powerpc/vec_rotate-3.c: New test.
* gcc.target/powerpc/vec_rotate-4.c: New test.
2019-08-07 Alexandre Oliva <oliva@adacore.com>
* gcc.target/i386/math_m_pi.h: New.

39
gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c Normal file
View file

@ -0,0 +1,39 @@
/* { dg-options "-O3" } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* Check vectorizer can exploit vector rotation instructions on Power, mainly
for the case rotation count is const number.
Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */
#define N 256
unsigned int suw[N], ruw[N];
unsigned short suh[N], ruh[N];
unsigned char sub[N], rub[N];
void
testUW ()
{
for (int i = 0; i < 256; ++i)
ruw[i] = (suw[i] >> 8) | (suw[i] << (sizeof (suw[0]) * 8 - 8));
}
void
testUH ()
{
for (int i = 0; i < 256; ++i)
ruh[i] = (unsigned short) (suh[i] >> 9)
| (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - 9));
}
void
testUB ()
{
for (int i = 0; i < 256; ++i)
rub[i] = (unsigned char) (sub[i] >> 5)
| (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - 5));
}
/* { dg-final { scan-assembler {\mvrlw\M} } } */
/* { dg-final { scan-assembler {\mvrlh\M} } } */
/* { dg-final { scan-assembler {\mvrlb\M} } } */

18
gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c Normal file
View file

@ -0,0 +1,18 @@
/* { dg-options "-O3 -mdejagnu-cpu=power8" } */
/* Check vectorizer can exploit vector rotation instructions on Power8, mainly
for the case rotation count is const number.
Check for vrld which is available on Power8 and above. */
#define N 256
unsigned long long sud[N], rud[N];
void
testULL ()
{
for (int i = 0; i < 256; ++i)
rud[i] = (sud[i] >> 8) | (sud[i] << (sizeof (sud[0]) * 8 - 8));
}
/* { dg-final { scan-assembler {\mvrld\M} } } */

40
gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c Normal file
View file

@ -0,0 +1,40 @@
/* { dg-options "-O3" } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* Check vectorizer can exploit vector rotation instructions on Power, mainly
for the case rotation count isn't const number.
Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */
#define N 256
unsigned int suw[N], ruw[N];
unsigned short suh[N], ruh[N];
unsigned char sub[N], rub[N];
extern unsigned char rot_cnt;
void
testUW ()
{
for (int i = 0; i < 256; ++i)
ruw[i] = (suw[i] >> rot_cnt) | (suw[i] << (sizeof (suw[0]) * 8 - rot_cnt));
}
void
testUH ()
{
for (int i = 0; i < 256; ++i)
ruh[i] = (unsigned short) (suh[i] >> rot_cnt)
| (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - rot_cnt));
}
void
testUB ()
{
for (int i = 0; i < 256; ++i)
rub[i] = (unsigned char) (sub[i] >> rot_cnt)
| (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - rot_cnt));
}
/* { dg-final { scan-assembler {\mvrlw\M} } } */
/* { dg-final { scan-assembler {\mvrlh\M} } } */
/* { dg-final { scan-assembler {\mvrlb\M} } } */

19
gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c Normal file
View file

@ -0,0 +1,19 @@
/* { dg-options "-O3 -mdejagnu-cpu=power8" } */
/* Check vectorizer can exploit vector rotation instructions on Power8, mainly
for the case rotation count isn't const number.
Check for vrld which is available on Power8 and above. */
#define N 256
unsigned long long sud[N], rud[N];
extern unsigned char rot_cnt;
void
testULL ()
{
for (int i = 0; i < 256; ++i)
rud[i] = (sud[i] >> rot_cnt) | (sud[i] << (sizeof (sud[0]) * 8 - rot_cnt));
}
/* { dg-final { scan-assembler {\mvrld\M} } } */