PR target/103069: Relax cmpxchg loop for x86 target
From the CPU's point of view, getting a cache line for writing is more expensive than reading. See Appendix A.2 Spinlock in: https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ xeon-lock-scaling-analysis-paper.pdf The full compare and swap will grab the cache line exclusive and causes excessive cache line bouncing. The atomic_fetch_{or,xor,and,nand} builtins generates cmpxchg loop under -march=x86-64 like: movl v(%rip), %eax .L2: movl %eax, %ecx movl %eax, %edx orl $1, %ecx lock cmpxchgl %ecx, v(%rip) jne .L2 movl %edx, %eax andl $1, %eax ret To relax above loop, GCC should first emit a normal load, check and jump to .L2 if cmpxchgl may fail. Before jump to .L2, PAUSE should be inserted to yield the CPU to another hyperthread and to save power, so the code is like .L84: movl (%rdi), %ecx movl %eax, %edx orl %esi, %edx cmpl %eax, %ecx jne .L82 lock cmpxchgl %edx, (%rdi) jne .L84 .L82: rep nop jmp .L84 This patch adds corresponding atomic_fetch_op expanders to insert load/ compare and pause for all the atomic logic fetch builtins. Add flag -mrelax-cmpxchg-loop to control whether to generate relaxed loop. gcc/ChangeLog: PR target/103069 * config/i386/i386-expand.c (ix86_expand_atomic_fetch_op_loop): New expand function. * config/i386/i386-options.c (ix86_target_string): Add -mrelax-cmpxchg-loop flag. (ix86_valid_target_attribute_inner_p): Likewise. * config/i386/i386-protos.h (ix86_expand_atomic_fetch_op_loop): New expand function prototype. * config/i386/i386.opt: Add -mrelax-cmpxchg-loop. * config/i386/sync.md (atomic_fetch_<logic><mode>): New expander for SI,HI,QI modes. (atomic_<logic>_fetch<mode>): Likewise. (atomic_fetch_nand<mode>): Likewise. (atomic_nand_fetch<mode>): Likewise. (atomic_fetch_<logic><mode>): New expander for DI,TI modes. (atomic_<logic>_fetch<mode>): Likewise. (atomic_fetch_nand<mode>): Likewise. (atomic_nand_fetch<mode>): Likewise. * doc/invoke.texi: Document -mrelax-cmpxchg-loop. gcc/testsuite/ChangeLog: PR target/103069 * gcc.target/i386/pr103069-1.c: New test. * gcc.target/i386/pr103069-2.c: Ditto.
This commit is contained in:
Hongyu Wang
parent
d1ca8aeaf3
commit
4d281ff7dd
8 changed files with 318 additions and 2 deletions
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@ -23138,4 +23138,80 @@ ix86_expand_divmod_libfunc (rtx libfunc, machine_mode mode,
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*rem_p = rem;
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}
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void ix86_expand_atomic_fetch_op_loop (rtx target, rtx mem, rtx val,
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enum rtx_code code, bool after,
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bool doubleword)
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{
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rtx old_reg, new_reg, old_mem, success, oldval, new_mem;
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rtx_code_label *loop_label, *pause_label;
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machine_mode mode = GET_MODE (target);
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old_reg = gen_reg_rtx (mode);
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new_reg = old_reg;
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loop_label = gen_label_rtx ();
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pause_label = gen_label_rtx ();
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old_mem = copy_to_reg (mem);
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emit_label (loop_label);
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emit_move_insn (old_reg, old_mem);
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/* return value for atomic_fetch_op. */
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if (!after)
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emit_move_insn (target, old_reg);
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if (code == NOT)
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{
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new_reg = expand_simple_binop (mode, AND, new_reg, val, NULL_RTX,
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true, OPTAB_LIB_WIDEN);
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new_reg = expand_simple_unop (mode, code, new_reg, NULL_RTX, true);
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}
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else
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new_reg = expand_simple_binop (mode, code, new_reg, val, NULL_RTX,
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true, OPTAB_LIB_WIDEN);
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/* return value for atomic_op_fetch. */
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if (after)
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emit_move_insn (target, new_reg);
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/* Load memory again inside loop. */
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new_mem = copy_to_reg (mem);
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/* Compare mem value with expected value. */
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if (doubleword)
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{
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machine_mode half_mode = (mode == DImode)? SImode : DImode;
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rtx low_new_mem = gen_lowpart (half_mode, new_mem);
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rtx low_old_mem = gen_lowpart (half_mode, old_mem);
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rtx high_new_mem = gen_highpart (half_mode, new_mem);
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rtx high_old_mem = gen_highpart (half_mode, old_mem);
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emit_cmp_and_jump_insns (low_new_mem, low_old_mem, NE, NULL_RTX,
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half_mode, 1, pause_label,
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profile_probability::guessed_never ());
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emit_cmp_and_jump_insns (high_new_mem, high_old_mem, NE, NULL_RTX,
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half_mode, 1, pause_label,
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profile_probability::guessed_never ());
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}
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else
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emit_cmp_and_jump_insns (new_mem, old_mem, NE, NULL_RTX,
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GET_MODE (old_mem), 1, pause_label,
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profile_probability::guessed_never ());
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success = NULL_RTX;
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oldval = old_mem;
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expand_atomic_compare_and_swap (&success, &oldval, mem, old_reg,
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new_reg, false, MEMMODEL_SYNC_SEQ_CST,
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MEMMODEL_RELAXED);
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if (oldval != old_mem)
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emit_move_insn (old_mem, oldval);
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emit_cmp_and_jump_insns (success, const0_rtx, EQ, const0_rtx,
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GET_MODE (success), 1, loop_label,
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profile_probability::guessed_never ());
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/* If mem is not expected, pause and loop back. */
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emit_label (pause_label);
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emit_insn (gen_pause ());
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emit_jump_insn (gen_jump (loop_label));
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emit_barrier ();
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}
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#include "gt-i386-expand.h"
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@ -397,7 +397,8 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
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{ "-mstv", MASK_STV },
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{ "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD },
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{ "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE },
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{ "-mcall-ms2sysv-xlogues", MASK_CALL_MS2SYSV_XLOGUES }
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{ "-mcall-ms2sysv-xlogues", MASK_CALL_MS2SYSV_XLOGUES },
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{ "-mrelax-cmpxchg-loop", MASK_RELAX_CMPXCHG_LOOP }
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};
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/* Additional flag options. */
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@ -1092,6 +1093,10 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
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IX86_ATTR_IX86_YES ("general-regs-only",
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OPT_mgeneral_regs_only,
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OPTION_MASK_GENERAL_REGS_ONLY),
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IX86_ATTR_YES ("relax-cmpxchg-loop",
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OPT_mrelax_cmpxchg_loop,
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MASK_RELAX_CMPXCHG_LOOP),
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};
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location_t loc
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@ -217,6 +217,8 @@ extern void ix86_move_vector_high_sse_to_mmx (rtx);
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extern void ix86_split_mmx_pack (rtx[], enum rtx_code);
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extern void ix86_split_mmx_punpck (rtx[], bool);
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extern void ix86_expand_avx_vzeroupper (void);
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extern void ix86_expand_atomic_fetch_op_loop (rtx, rtx, rtx, enum rtx_code,
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bool, bool);
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#ifdef TREE_CODE
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extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
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@ -404,6 +404,10 @@ momit-leaf-frame-pointer
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Target Mask(OMIT_LEAF_FRAME_POINTER) Save
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Omit the frame pointer in leaf functions.
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mrelax-cmpxchg-loop
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Target Mask(RELAX_CMPXCHG_LOOP) Save
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Relax cmpxchg loop for atomic_fetch_{or,xor,and,nand} by adding load and cmp before cmpxchg, execute pause and loop back to load and compare if load value is not expected.
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mpc32
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Target RejectNegative
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Set 80387 floating-point precision to 32-bit.
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@ -525,6 +525,123 @@
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(set (reg:CCZ FLAGS_REG)
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(unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG))])])
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(define_expand "atomic_fetch_<logic><mode>"
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[(match_operand:SWI124 0 "register_operand")
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(any_logic:SWI124
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(match_operand:SWI124 1 "memory_operand")
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(match_operand:SWI124 2 "register_operand"))
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(match_operand:SI 3 "const_int_operand")]
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"TARGET_CMPXCHG && TARGET_RELAX_CMPXCHG_LOOP"
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{
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ix86_expand_atomic_fetch_op_loop (operands[0], operands[1],
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operands[2], <CODE>, false,
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false);
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DONE;
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})
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(define_expand "atomic_<logic>_fetch<mode>"
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[(match_operand:SWI124 0 "register_operand")
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(any_logic:SWI124
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(match_operand:SWI124 1 "memory_operand")
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(match_operand:SWI124 2 "register_operand"))
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(match_operand:SI 3 "const_int_operand")]
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"TARGET_CMPXCHG && TARGET_RELAX_CMPXCHG_LOOP"
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{
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ix86_expand_atomic_fetch_op_loop (operands[0], operands[1],
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operands[2], <CODE>, true,
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false);
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DONE;
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})
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(define_expand "atomic_fetch_nand<mode>"
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[(match_operand:SWI124 0 "register_operand")
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(match_operand:SWI124 1 "memory_operand")
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(match_operand:SWI124 2 "register_operand")
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(match_operand:SI 3 "const_int_operand")]
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"TARGET_CMPXCHG && TARGET_RELAX_CMPXCHG_LOOP"
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{
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ix86_expand_atomic_fetch_op_loop (operands[0], operands[1],
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operands[2], NOT, false,
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false);
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DONE;
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})
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(define_expand "atomic_nand_fetch<mode>"
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[(match_operand:SWI124 0 "register_operand")
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(match_operand:SWI124 1 "memory_operand")
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(match_operand:SWI124 2 "register_operand")
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(match_operand:SI 3 "const_int_operand")]
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"TARGET_CMPXCHG && TARGET_RELAX_CMPXCHG_LOOP"
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{
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ix86_expand_atomic_fetch_op_loop (operands[0], operands[1],
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operands[2], NOT, true,
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false);
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DONE;
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})
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(define_expand "atomic_fetch_<logic><mode>"
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[(match_operand:CASMODE 0 "register_operand")
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(any_logic:CASMODE
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(match_operand:CASMODE 1 "memory_operand")
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(match_operand:CASMODE 2 "register_operand"))
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(match_operand:SI 3 "const_int_operand")]
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"TARGET_CMPXCHG && TARGET_RELAX_CMPXCHG_LOOP"
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{
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bool doubleword = (<MODE>mode == DImode && !TARGET_64BIT)
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|| (<MODE>mode == TImode);
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ix86_expand_atomic_fetch_op_loop (operands[0], operands[1],
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operands[2], <CODE>, false,
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doubleword);
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DONE;
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})
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(define_expand "atomic_<logic>_fetch<mode>"
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[(match_operand:CASMODE 0 "register_operand")
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(any_logic:CASMODE
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(match_operand:CASMODE 1 "memory_operand")
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(match_operand:CASMODE 2 "register_operand"))
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(match_operand:SI 3 "const_int_operand")]
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"TARGET_CMPXCHG && TARGET_RELAX_CMPXCHG_LOOP"
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{
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bool doubleword = (<MODE>mode == DImode && !TARGET_64BIT)
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|| (<MODE>mode == TImode);
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ix86_expand_atomic_fetch_op_loop (operands[0], operands[1],
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operands[2], <CODE>, true,
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doubleword);
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DONE;
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})
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(define_expand "atomic_fetch_nand<mode>"
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[(match_operand:CASMODE 0 "register_operand")
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(match_operand:CASMODE 1 "memory_operand")
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(match_operand:CASMODE 2 "register_operand")
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(match_operand:SI 3 "const_int_operand")]
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"TARGET_CMPXCHG && TARGET_RELAX_CMPXCHG_LOOP"
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{
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bool doubleword = (<MODE>mode == DImode && !TARGET_64BIT)
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|| (<MODE>mode == TImode);
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ix86_expand_atomic_fetch_op_loop (operands[0], operands[1],
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operands[2], NOT, false,
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doubleword);
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DONE;
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})
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(define_expand "atomic_nand_fetch<mode>"
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[(match_operand:CASMODE 0 "register_operand")
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(match_operand:CASMODE 1 "memory_operand")
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(match_operand:CASMODE 2 "register_operand")
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(match_operand:SI 3 "const_int_operand")]
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"TARGET_CMPXCHG && TARGET_RELAX_CMPXCHG_LOOP"
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{
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bool doubleword = (<MODE>mode == DImode && !TARGET_64BIT)
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|| (<MODE>mode == TImode);
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ix86_expand_atomic_fetch_op_loop (operands[0], operands[1],
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operands[2], NOT, true,
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doubleword);
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DONE;
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})
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;; For operand 2 nonmemory_operand predicate is used instead of
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;; register_operand to allow combiner to better optimize atomic
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;; additions of constants.
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@ -1423,7 +1423,7 @@ See RS/6000 and PowerPC Options.
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-mstack-protector-guard-reg=@var{reg} @gol
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-mstack-protector-guard-offset=@var{offset} @gol
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-mstack-protector-guard-symbol=@var{symbol} @gol
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-mgeneral-regs-only -mcall-ms2sysv-xlogues @gol
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-mgeneral-regs-only -mcall-ms2sysv-xlogues -mrelax-cmpxchg-loop @gol
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-mindirect-branch=@var{choice} -mfunction-return=@var{choice} @gol
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-mindirect-branch-register -mneeded}
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@ -32330,6 +32330,13 @@ Generate code that uses only the general-purpose registers. This
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prevents the compiler from using floating-point, vector, mask and bound
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registers.
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@item -mrelax-cmpxchg-loop
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@opindex mrelax-cmpxchg-loop
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Relax cmpxchg loop by emitting an early load and compare before cmpxchg,
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execute pause if load value is not expected. This reduces excessive
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cachline bouncing when and works for all atomic logic fetch builtins
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that generates compare and swap loop.
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@item -mindirect-branch=@var{choice}
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@opindex mindirect-branch
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Convert indirect call and jump with @var{choice}. The default is
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35
gcc/testsuite/gcc.target/i386/pr103069-1.c
Normal file
35
gcc/testsuite/gcc.target/i386/pr103069-1.c
Normal file
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@ -0,0 +1,35 @@
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/* PR target/103068 */
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/* { dg-do compile } */
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/* { dg-additional-options "-O2 -march=x86-64 -mtune=generic -mrelax-cmpxchg-loop" } */
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/* { dg-final { scan-assembler-times "rep;?\[ \\t\]+nop" 32 } } */
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#include <stdint.h>
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#define FUNC_ATOMIC(TYPE, OP) \
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__attribute__ ((noinline, noclone)) \
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TYPE f_##TYPE##_##OP##_fetch (TYPE *a, TYPE b) \
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{ \
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return __atomic_##OP##_fetch (a, b, __ATOMIC_RELAXED); \
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} \
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__attribute__ ((noinline, noclone)) \
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TYPE f_##TYPE##_fetch_##OP (TYPE *a, TYPE b) \
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{ \
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return __atomic_fetch_##OP (a, b, __ATOMIC_RELAXED); \
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}
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FUNC_ATOMIC (int64_t, and)
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FUNC_ATOMIC (int64_t, nand)
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FUNC_ATOMIC (int64_t, or)
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FUNC_ATOMIC (int64_t, xor)
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FUNC_ATOMIC (int, and)
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FUNC_ATOMIC (int, nand)
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FUNC_ATOMIC (int, or)
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FUNC_ATOMIC (int, xor)
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FUNC_ATOMIC (short, and)
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FUNC_ATOMIC (short, nand)
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FUNC_ATOMIC (short, or)
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FUNC_ATOMIC (short, xor)
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FUNC_ATOMIC (char, and)
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FUNC_ATOMIC (char, nand)
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FUNC_ATOMIC (char, or)
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FUNC_ATOMIC (char, xor)
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70
gcc/testsuite/gcc.target/i386/pr103069-2.c
Normal file
70
gcc/testsuite/gcc.target/i386/pr103069-2.c
Normal file
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@ -0,0 +1,70 @@
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/* PR target/103068 */
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/* { dg-do compile } */
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/* { dg-additional-options "-O2 -march=x86-64 -mtune=generic" } */
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#include <stdlib.h>
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#include "pr103069-1.c"
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#define FUNC_ATOMIC_RELAX(TYPE, OP) \
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__attribute__ ((noinline, noclone, target ("relax-cmpxchg-loop"))) \
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TYPE relax_##TYPE##_##OP##_fetch (TYPE *a, TYPE b) \
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{ \
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return __atomic_##OP##_fetch (a, b, __ATOMIC_RELAXED); \
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} \
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__attribute__ ((noinline, noclone, target ("relax-cmpxchg-loop"))) \
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TYPE relax_##TYPE##_fetch_##OP (TYPE *a, TYPE b) \
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{ \
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return __atomic_fetch_##OP (a, b, __ATOMIC_RELAXED); \
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}
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FUNC_ATOMIC_RELAX (int64_t, and)
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FUNC_ATOMIC_RELAX (int64_t, nand)
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FUNC_ATOMIC_RELAX (int64_t, or)
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FUNC_ATOMIC_RELAX (int64_t, xor)
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FUNC_ATOMIC_RELAX (int, and)
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FUNC_ATOMIC_RELAX (int, nand)
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FUNC_ATOMIC_RELAX (int, or)
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FUNC_ATOMIC_RELAX (int, xor)
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FUNC_ATOMIC_RELAX (short, and)
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FUNC_ATOMIC_RELAX (short, nand)
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FUNC_ATOMIC_RELAX (short, or)
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FUNC_ATOMIC_RELAX (short, xor)
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FUNC_ATOMIC_RELAX (char, and)
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FUNC_ATOMIC_RELAX (char, nand)
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FUNC_ATOMIC_RELAX (char, or)
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FUNC_ATOMIC_RELAX (char, xor)
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#define TEST_ATOMIC_FETCH_LOGIC(TYPE, OP) \
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{ \
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TYPE a = 11, b = 101, res, exp; \
|
||||
res = relax_##TYPE##_##OP##_fetch (&a, b); \
|
||||
exp = f_##TYPE##_##OP##_fetch (&a, b); \
|
||||
if (res != exp) \
|
||||
abort (); \
|
||||
a = 21, b = 92; \
|
||||
res = relax_##TYPE##_fetch_##OP (&a, b); \
|
||||
exp = f_##TYPE##_fetch_##OP (&a, b); \
|
||||
if (res != exp) \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
int main (void)
|
||||
{
|
||||
TEST_ATOMIC_FETCH_LOGIC (int64_t, and)
|
||||
TEST_ATOMIC_FETCH_LOGIC (int64_t, nand)
|
||||
TEST_ATOMIC_FETCH_LOGIC (int64_t, or)
|
||||
TEST_ATOMIC_FETCH_LOGIC (int64_t, xor)
|
||||
TEST_ATOMIC_FETCH_LOGIC (int, and)
|
||||
TEST_ATOMIC_FETCH_LOGIC (int, nand)
|
||||
TEST_ATOMIC_FETCH_LOGIC (int, or)
|
||||
TEST_ATOMIC_FETCH_LOGIC (int, xor)
|
||||
TEST_ATOMIC_FETCH_LOGIC (short, and)
|
||||
TEST_ATOMIC_FETCH_LOGIC (short, nand)
|
||||
TEST_ATOMIC_FETCH_LOGIC (short, or)
|
||||
TEST_ATOMIC_FETCH_LOGIC (short, xor)
|
||||
TEST_ATOMIC_FETCH_LOGIC (char, and)
|
||||
TEST_ATOMIC_FETCH_LOGIC (char, nand)
|
||||
TEST_ATOMIC_FETCH_LOGIC (char, or)
|
||||
TEST_ATOMIC_FETCH_LOGIC (char, xor)
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue