i386: x r<< (c - y) to x r>> y etc. optimization [PR117930]
The following patch optimizes x r<< (c - y) to x r>> y, x r>> (c - y) to x r<< y, x r<< (c + y) to x r<< y and x r>> (c + y) to x r>> y if c is a multiple of x's bitsize. 2024-12-07 Jakub Jelinek <jakub@redhat.com> PR target/117930 * config/i386/i386.md (crotate): New define_code_attr. (*<insn><mode>3_add, *<insn><mode>3_add_1, *<insn><mode>3_sub, *<insn><mode>3_sub_1): New define_insn_and_split patterns plus following define_split for constant first input operand. * gcc.target/i386/pr117930.c: New test.
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Jakub Jelinek
Jakub Jelinek
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2 changed files with 259 additions and 0 deletions
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@ -1079,6 +1079,9 @@
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;; Base name for insn mnemonic.
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(define_code_attr rotate [(rotate "rol") (rotatert "ror")])
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;; Counter rotate.
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(define_code_attr crotate [(rotate "rotatert") (rotatert "rotate")])
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;; Mapping of abs neg operators
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(define_code_iterator absneg [abs neg])
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@ -18216,6 +18219,144 @@
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(any_rotate:SWI (match_dup 4) (match_dup 2)))]
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"operands[4] = gen_reg_rtx (<MODE>mode);")
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(define_insn_and_split "*<insn><mode>3_add"
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[(set (match_operand:SWI 0 "nonimmediate_operand")
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(any_rotate:SWI
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(match_operand:SWI 1 "nonimmediate_operand")
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(subreg:QI
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(plus
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(match_operand 2 "int_nonimmediate_operand")
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(match_operand 3 "const_int_operand")) 0)))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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&& (INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT - 1)) == 0
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(parallel
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[(set (match_dup 0)
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(any_rotate:SWI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
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operands[2] = gen_lowpart (QImode, operands[2]);
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})
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(define_split
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[(set (match_operand:SWI 0 "register_operand")
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(any_rotate:SWI
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(match_operand:SWI 1 "const_int_operand")
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(subreg:QI
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(plus
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(match_operand 2 "int248_register_operand")
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(match_operand 3 "const_int_operand")) 0)))]
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"(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT - 1)) == 0"
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[(set (match_dup 4) (match_dup 1))
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(set (match_dup 0)
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(any_rotate:SWI (match_dup 4) (subreg:QI (match_dup 2) 0)))]
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"operands[4] = gen_reg_rtx (<MODE>mode);")
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(define_insn_and_split "*<insn><mode>3_add_1"
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[(set (match_operand:SWI 0 "nonimmediate_operand")
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(any_rotate:SWI
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(match_operand:SWI 1 "nonimmediate_operand")
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(plus:QI
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(match_operand:QI 2 "nonimmediate_operand")
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(match_operand:QI 3 "const_int_operand"))))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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&& (INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT - 1)) == 0
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(parallel
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[(set (match_dup 0)
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(any_rotate:SWI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);")
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(define_split
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[(set (match_operand:SWI 0 "register_operand")
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(any_rotate:SWI
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(match_operand:SWI 1 "const_int_operand")
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(plus:QI
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(match_operand:QI 2 "register_operand")
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(match_operand:QI 3 "const_int_operand"))))]
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"(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT - 1)) == 0"
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[(set (match_dup 4) (match_dup 1))
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(set (match_dup 0)
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(any_rotate:SWI (match_dup 4) (match_dup 2)))]
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"operands[4] = gen_reg_rtx (<MODE>mode);")
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(define_insn_and_split "*<insn><mode>3_sub"
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[(set (match_operand:SWI 0 "nonimmediate_operand")
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(any_rotate:SWI
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(match_operand:SWI 1 "nonimmediate_operand")
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(subreg:QI
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(minus
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(match_operand 3 "const_int_operand")
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(match_operand 2 "int_nonimmediate_operand")) 0)))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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&& (INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT - 1)) == 0
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(parallel
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[(set (match_dup 0)
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(<crotate>:SWI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
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operands[2] = gen_lowpart (QImode, operands[2]);
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})
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(define_split
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[(set (match_operand:SWI 0 "register_operand")
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(any_rotate:SWI
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(match_operand:SWI 1 "const_int_operand")
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(subreg:QI
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(minus
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(match_operand 3 "const_int_operand")
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(match_operand 2 "int248_register_operand")) 0)))]
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"(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT - 1)) == 0"
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[(set (match_dup 4) (match_dup 1))
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(set (match_dup 0)
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(<crotate>:SWI (match_dup 4) (subreg:QI (match_dup 2) 0)))]
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"operands[4] = gen_reg_rtx (<MODE>mode);")
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(define_insn_and_split "*<insn><mode>3_sub_1"
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[(set (match_operand:SWI 0 "nonimmediate_operand")
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(any_rotate:SWI
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(match_operand:SWI 1 "nonimmediate_operand")
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(minus:QI
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(match_operand:QI 3 "const_int_operand")
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(match_operand:QI 2 "nonimmediate_operand"))))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
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&& (INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT - 1)) == 0
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&& ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(parallel
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[(set (match_dup 0)
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(<crotate>:SWI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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"operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);")
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(define_split
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[(set (match_operand:SWI 0 "register_operand")
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(any_rotate:SWI
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(match_operand:SWI 1 "const_int_operand")
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(minus:QI
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(match_operand:QI 3 "const_int_operand")
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(match_operand:QI 2 "register_operand"))))]
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"(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT - 1)) == 0"
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[(set (match_dup 4) (match_dup 1))
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(set (match_dup 0)
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(<crotate>:SWI (match_dup 4) (match_dup 2)))]
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"operands[4] = gen_reg_rtx (<MODE>mode);")
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;; Implement rotation using two double-precision
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;; shift instructions and a scratch register.
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118
gcc/testsuite/gcc.target/i386/pr117930.c
Normal file
118
gcc/testsuite/gcc.target/i386/pr117930.c
Normal file
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@ -0,0 +1,118 @@
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/* PR target/117930 */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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/* { dg-final { scan-assembler-not "sub\[bwlq\]\t" } } */
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/* { dg-final { scan-assembler-not "add\[bwlq\]\t" } } */
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/* { dg-final { scan-assembler-not "lea\[lq\]\t" } } */
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static inline
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unsigned lrotate (unsigned x, int t)
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{
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unsigned tl = x << t;
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unsigned th = x >> (-t & 31);
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return tl | th;
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}
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static inline
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unsigned rrotate (unsigned x, int t)
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{
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unsigned tl = x >> t;
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unsigned th = x << (-t & 31);
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return tl | th;
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}
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unsigned
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f1 (unsigned x, int t)
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{
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return lrotate (x, 32 - t);
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}
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unsigned
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f2 (unsigned x, int t)
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{
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return lrotate (x, 64 - t);
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}
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unsigned
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f3 (unsigned x, int t)
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{
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return lrotate (x, 32 + t);
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}
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unsigned
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f4 (unsigned x, int t)
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{
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return lrotate (x, 64 + t);
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}
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unsigned
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f5 (unsigned x, int t)
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{
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return rrotate (x, 32 - t);
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}
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unsigned
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f6 (unsigned x, int t)
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{
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return rrotate (x, 64 - t);
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}
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unsigned
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f7 (unsigned x, int t)
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{
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return rrotate (x, 32 + t);
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}
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unsigned
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f8 (unsigned x, int t)
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{
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return rrotate (x, 64 + t);
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}
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unsigned
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f9 (int t)
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{
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return lrotate (0xdeadbeefU, 32 - t);
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}
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unsigned
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f10 (int t)
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{
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return lrotate (0xdeadbeefU, 64 - t);
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}
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unsigned
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f11 (int t)
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{
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return lrotate (0xdeadbeefU, 32 + t);
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}
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unsigned
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f12 (int t)
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{
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return lrotate (0xdeadbeefU, 64 + t);
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}
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unsigned
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f13 (int t)
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{
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return rrotate (0xdeadbeefU, 32 - t);
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}
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unsigned
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f14 (int t)
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{
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return rrotate (0xdeadbeefU, 64 - t);
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}
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unsigned
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f15 (int t)
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{
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return rrotate (0xdeadbeefU, 32 + t);
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}
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unsigned
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f16 (int t)
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{
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return rrotate (0xdeadbeefU, 64 + t);
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}
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