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Set znver5 issue rate to 4.

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this patch sets issue rate of znver5 to 4.  With current model, unless a reservation is
missing, we will never issue more than 4 instructions per cycle since that is the limit
of decoders and the model does not take into acount the fact that typically code is run
from op cache.

gcc/ChangeLog:

	* config/i386/x86-tune-sched.cc (ix86_issue_rate): Set
	to 4 for znver5.
This commit is contained in:
Jan Hubicka 2025-04-15 19:09:20 +02:00
parent e2011ab13d
commit 4a01869b96
1 changed files with 8 additions and 7 deletions
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15
gcc/config/i386/x86-tune-sched.cc
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@ -81,6 +81,14 @@ ix86_issue_rate (void)
case PROCESSOR_YONGFENG:
case PROCESSOR_SHIJIDADAO:
case PROCESSOR_GENERIC:
/* For znver5 decoder can handle 4 or 8 instructions per cycle,
op cache 12 instruction/cycle, dispatch 8 instructions
integer rename 8 instructions and Fp 6 instructions.
The scheduler, without understanding out of order nature of the CPU
is not going to be able to use more than 4 instructions since that
is limits of the decoders. */
case PROCESSOR_ZNVER5:
return 4;
case PROCESSOR_ICELAKE_CLIENT:
@ -91,13 +99,6 @@ ix86_issue_rate (void)
return 5;
case PROCESSOR_SAPPHIRERAPIDS:
/* For znver5 decoder can handle 4 or 8 instructions per cycle,
op cache 12 instruction/cycle, dispatch 8 instructions
integer rename 8 instructions and Fp 6 instructions.
The scheduler, without understanding out of order nature of the CPU
is unlikely going to be able to fill all of these. */
case PROCESSOR_ZNVER5:
return 6;
default: