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h8300.md (bsetqi_msx, [...]): Added condition to disallow non-identical memory locations.

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* config/h8300/h8300.md (bsetqi_msx, bclrqi_msx, bnotqi_msx): Added 
	condition to disallow non-identical memory locations.
	(*andqi3_2, andqi3_1, iorqi3_1, xorqi3_1): Reorder insn to give
	preference to bit manipulation instructions.
	* gcc.dg/h8300-bit-insn-ice2.2: New testcase.

From-SVN: r174986
This commit is contained in:
Kaushik Phatak 2011-06-13 09:31:41 +00:00 • committed by Kaushik Phatak
parent 9aa3f5c58c
commit 495f8c142d
3 changed files with 76 additions and 30 deletions
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8
gcc/ChangeLog
View file

@ -1,3 +1,11 @@
2011-06-13 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
* config/h8300/h8300.md (bsetqi_msx, bclrqi_msx, bnotqi_msx): Added
condition to disallow non-identical memory locations.
(*andqi3_2, andqi3_1, iorqi3_1, xorqi3_1): Reorder insn to give
preference to bit manipulation instructions.
* gcc.dg/h8300-bit-insn-ice2.2: New testcase.
2011-06-13 Jan Hubicka <jh@suse.cz>
* cgraph.c (cgraph_for_node_thunks_and_aliases,

68
gcc/config/h8300/h8300.md
View file

@ -1767,7 +1767,8 @@
[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
(and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
(match_operand:QI 2 "single_zero_operand" "Y0")))]
"TARGET_H8300SX"
"TARGET_H8300SX
&& rtx_equal_p(operands[0], operands[1])"
"bclr\\t%W2,%0"
[(set_attr "length" "8")])
@ -1800,29 +1801,31 @@
"TARGET_H8300SX"
"bclr\\t%W2,%0"
[(set_attr "length" "8")])
(define_insn "*andqi3_2"
[(set (match_operand:QI 0 "bit_operand" "=rQ,r")
(and:QI (match_operand:QI 1 "bit_operand" "%0,WU")
(match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))]
[(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
(and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
(match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
"TARGET_H8300SX"
"@
and %X2,%X0
bfld %2,%1,%R0"
[(set_attr "length" "*,8")
(set_attr "length_table" "logicb,*")
(set_attr "cc" "set_znv,none_0hit")])
bclr\\t %W2,%R0
and %X2,%X0
bfld %2,%1,%R0"
[(set_attr "length" "8,*,8")
(set_attr "length_table" "*,logicb,*")
(set_attr "cc" "none_0hit,set_znv,none_0hit")])
(define_insn "andqi3_1"
[(set (match_operand:QI 0 "bit_operand" "=r,U")
[(set (match_operand:QI 0 "bit_operand" "=U,r")
(and:QI (match_operand:QI 1 "bit_operand" "%0,0")
(match_operand:QI 2 "h8300_src_operand" "rn,n")))]
(match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
"register_operand (operands[0], QImode)
|| single_zero_operand (operands[2], QImode)"
"@
and %X2,%X0
bclr %W2,%R0"
bclr %W2,%R0
and %X2,%X0"
[(set_attr "length" "2,8")
(set_attr "cc" "set_znv,none_0hit")])
(set_attr "cc" "none_0hit,set_znv")])
(define_expand "andqi3"
[(set (match_operand:QI 0 "register_operand" "")
@ -1903,11 +1906,13 @@
;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------
(define_insn "bsetqi_msx"
[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
(ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
(match_operand:QI 2 "single_one_operand" "Y2")))]
"TARGET_H8300SX"
"TARGET_H8300SX
&& rtx_equal_p(operands[0], operands[1])"
"bset\\t%V2,%0"
[(set_attr "length" "8")])
@ -1942,17 +1947,18 @@
[(set_attr "length" "8")])
(define_insn "iorqi3_1"
[(set (match_operand:QI 0 "bit_operand" "=rQ,U")
[(set (match_operand:QI 0 "bit_operand" "=U,rQ")
(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
(match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
(match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
"TARGET_H8300SX || register_operand (operands[0], QImode)
|| single_one_operand (operands[2], QImode)"
"@
or\\t%X2,%X0
bset\\t%V2,%R0"
[(set_attr "length" "*,8")
(set_attr "length_table" "logicb,*")
(set_attr "cc" "set_znv,none_0hit")])
bset\\t%V2,%R0
or\\t%X2,%X0"
[(set_attr "length" "8,*")
(set_attr "length_table" "*,logicb")
(set_attr "cc" "none_0hit,set_znv")])
(define_expand "iorqi3"
[(set (match_operand:QI 0 "register_operand" "")
@ -1982,7 +1988,8 @@
[(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
(xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
(match_operand:QI 2 "single_one_operand" "Y2")))]
"TARGET_H8300SX"
"TARGET_H8300SX
&& rtx_equal_p(operands[0], operands[1])"
"bnot\\t%V2,%0"
[(set_attr "length" "8")])
@ -2017,17 +2024,18 @@
[(set_attr "length" "8")])
(define_insn "xorqi3_1"
[(set (match_operand:QI 0 "bit_operand" "=r,U")
[(set (match_operand:QI 0 "bit_operand" "=U,r")
(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
(match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
(match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
"TARGET_H8300SX || register_operand (operands[0], QImode)
|| single_one_operand (operands[2], QImode)"
"@
xor\\t%X2,%X0
bnot\\t%V2,%R0"
[(set_attr "length" "*,8")
(set_attr "length_table" "logicb,*")
(set_attr "cc" "set_znv,none_0hit")])
bnot\\t%V2,%R0
xor\\t%X2,%X0"
[(set_attr "length" "8,*")
(set_attr "length_table" "*,logicb")
(set_attr "cc" "none_0hit,set_znv")])
(define_expand "xorqi3"
[(set (match_operand:QI 0 "register_operand" "")

30
gcc/testsuite/gcc.dg/h8300-bit-insn-ice2.c Normal file
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@ -0,0 +1,30 @@
/* { dg-skip-if "" { "h8300*-*-*" } "*" "-msx*" } */
/* { dg-options "-O2" } */
/* ICE for bit instruction generation using 16-bit const */
#define MSTPCRA (*(volatile unsigned char*)0xFFFFC9)
#define MSTPCRA2 (*(volatile unsigned char*)0xFFFDC8)
int
main (void)
{
MSTPCRA = MSTPCRA2 & ~0x01;
MSTPCRA = MSTPCRA2 ^ ~0xFE;
MSTPCRA = MSTPCRA2 | ~0xFE;
return 0;
}
/* { dg-skip-if "" { "h8300*-*-*" } "*" "-msx*" } */
/* { dg-options "-O2" } */
/* ICE for bit instruction generation using 16-bit const */
#define MSTPCRA (*(volatile unsigned char*)0xFFFFC9)
#define MSTPCRA2 (*(volatile unsigned char*)0xFFFDC8)
int
main (void)
{
MSTPCRA = MSTPCRA2 & ~0x01;
MSTPCRA = MSTPCRA2 ^ ~0xFE;
MSTPCRA = MSTPCRA2 | ~0xFE;
return 0;
}