LoongArch: Redundant sign extension elimination optimization.
We found that the current combine optimization pass in gcc cannot handle
the following redundant sign extension situations:
(insn 77 76 78 5 (set (reg:SI 143)
(plus:SI (subreg/s/u:SI (reg/v:DI 104 [ len ]) 0)
(const_int 1 [0x1]))) {addsi3}
(expr_list:REG_DEAD (reg/v:DI 104 [ len ])
(nil)))
(insn 78 77 82 5 (set (reg/v:DI 104 [ len ])
(sign_extend:DI (reg:SI 143))) {extendsidi2}
(nil))
Because reg:SI 143 is not died or set in insn 78, no replacement merge will
be performed for the insn sequence. We adjusted the add template to eliminate
redundant sign extensions during the expand pass.
Adjusted based on upstream comments:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641988.html
gcc/ChangeLog:
* config/loongarch/loongarch.md (add<mode>3): Removed.
(*addsi3): New.
(addsi3): Ditto.
(adddi3): Ditto.
(*addsi3_extended): Removed.
(addsi3_extended): New.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/sign-extend.c: Moved to...
* gcc.target/loongarch/sign-extend-1.c: ...here.
* gcc.target/loongarch/sign-extend-2.c: New test.
This commit is contained in:
Li Wei
Lulu Cheng
parent
1a80e9558d
commit
493bebb3cd
3 changed files with 128 additions and 24 deletions
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@ -657,42 +657,87 @@
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[(set_attr "type" "fadd")
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(set_attr "mode" "<UNITMODE>")])
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(define_insn_and_split "add<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=r,r,r,r,r,r,r")
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(plus:GPR (match_operand:GPR 1 "register_operand" "r,r,r,r,r,r,r")
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(match_operand:GPR 2 "plus_<mode>_operand"
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"r,I,La,Lb,Lc,Ld,Le")))]
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(define_insn_and_split "*addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
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(plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r,r")
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(match_operand:SI 2 "plus_si_operand"
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"r,I,La,Lb,Le")))]
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""
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"@
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add.<d>\t%0,%1,%2
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addi.<d>\t%0,%1,%2
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add.w\t%0,%1,%2
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addi.w\t%0,%1,%2
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#
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* operands[2] = GEN_INT (INTVAL (operands[2]) / 65536); \
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return \"addu16i.d\t%0,%1,%2\";
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#"
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"CONST_INT_P (operands[2]) && !IMM12_INT (operands[2]) \
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&& !ADDU16I_OPERAND (INTVAL (operands[2]))"
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[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
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(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
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{
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loongarch_split_plus_constant (&operands[2], SImode);
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}
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[(set_attr "alu_type" "add")
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(set_attr "mode" "SI")
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(set_attr "insn_count" "1,1,2,1,2")])
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
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(plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r,r")
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(match_operand:SI 2 "plus_si_operand" "r,I,La,Le,Lb")))]
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"TARGET_64BIT"
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{
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if (CONST_INT_P (operands[2]) && !IMM12_INT (operands[2])
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&& ADDU16I_OPERAND (INTVAL (operands[2])))
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{
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rtx t1 = gen_reg_rtx (DImode);
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rtx t2 = gen_reg_rtx (DImode);
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rtx t3 = gen_reg_rtx (DImode);
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emit_insn (gen_extend_insn (t1, operands[1], DImode, SImode, 0));
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t2 = operands[2];
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emit_insn (gen_adddi3 (t3, t1, t2));
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t3 = gen_lowpart (SImode, t3);
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emit_move_insn (operands[0], t3);
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DONE;
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}
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else
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{
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rtx t = gen_reg_rtx (DImode);
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emit_insn (gen_addsi3_extended (t, operands[1], operands[2]));
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t = gen_lowpart (SImode, t);
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SUBREG_PROMOTED_VAR_P (t) = 1;
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SUBREG_PROMOTED_SET (t, SRP_SIGNED);
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emit_move_insn (operands[0], t);
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DONE;
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}
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})
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(define_insn_and_split "adddi3"
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[(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
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(plus:DI (match_operand:DI 1 "register_operand" "r,r,r,r,r,r")
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(match_operand:DI 2 "plus_di_operand"
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"r,I,La,Lb,Lc,Ld")))]
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"TARGET_64BIT"
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"@
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add.d\t%0,%1,%2
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addi.d\t%0,%1,%2
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#
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* operands[2] = GEN_INT (INTVAL (operands[2]) / 65536); \
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return \"addu16i.d\t%0,%1,%2\";
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#
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#
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#"
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"CONST_INT_P (operands[2]) && !IMM12_INT (operands[2]) \
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"&& CONST_INT_P (operands[2]) && !IMM12_INT (operands[2]) \
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&& !ADDU16I_OPERAND (INTVAL (operands[2]))"
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[(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
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(set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
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[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
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(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
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{
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loongarch_split_plus_constant (&operands[2], <MODE>mode);
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loongarch_split_plus_constant (&operands[2], DImode);
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}
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[(set_attr "alu_type" "add")
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(set_attr "mode" "<MODE>")
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(set_attr "insn_count" "1,1,2,1,2,2,2")
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(set (attr "enabled")
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(cond
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[(match_test "<MODE>mode != DImode && which_alternative == 4")
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(const_string "no")
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(match_test "<MODE>mode != DImode && which_alternative == 5")
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(const_string "no")
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(match_test "<MODE>mode != SImode && which_alternative == 6")
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(const_string "no")]
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(const_string "yes")))])
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(set_attr "mode" "DI")
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(set_attr "insn_count" "1,1,2,1,2,2")])
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(define_insn_and_split "*addsi3_extended"
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(define_insn_and_split "addsi3_extended"
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[(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
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(sign_extend:DI
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(plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
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59
gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
Normal file
59
gcc/testsuite/gcc.target/loongarch/sign-extend-2.c
Normal file
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@ -0,0 +1,59 @@
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/* { dg-do compile } */
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/* { dg-options "-mabi=lp64d -O2" } */
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/* { dg-final { scan-assembler-times "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" 1 } } */
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#include <stdint.h>
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#define my_min(x, y) ((x) < (y) ? (x) : (y))
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void
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bt_skip_func (const uint32_t len_limit, const uint32_t pos,
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const uint8_t *const cur, uint32_t cur_match,
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uint32_t *const son, const uint32_t cyclic_pos,
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const uint32_t cyclic_size)
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{
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uint32_t *ptr0 = son + (cyclic_pos << 1) + 1;
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uint32_t *ptr1 = son + (cyclic_pos << 1);
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uint32_t len0 = 0;
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uint32_t len1 = 0;
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while (1)
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{
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const uint32_t delta = pos - cur_match;
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uint32_t *pair
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= son
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+ ((cyclic_pos - delta + (delta > cyclic_pos ? cyclic_size : 0))
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<< 1);
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const uint8_t *pb = cur - delta;
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uint32_t len = my_min (len0, len1);
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if (pb[len] == cur[len])
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{
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while (++len != len_limit)
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if (pb[len] != cur[len])
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break;
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if (len == len_limit)
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{
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*ptr1 = pair[0];
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*ptr0 = pair[1];
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return;
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}
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}
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if (pb[len] < cur[len])
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{
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*ptr1 = cur_match;
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ptr1 = pair + 1;
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cur_match = *ptr1;
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len1 = len;
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}
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else
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{
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*ptr0 = cur_match;
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ptr0 = pair;
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cur_match = *ptr0;
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len0 = len;
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}
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}
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}
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