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sparc.c (emit_scc_insn): Remove direct support for EQ and GEU in DImode if TARGET_SUBXC.

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* config/sparc/sparc.c (emit_scc_insn): Remove direct support for EQ
	and GEU in DImode if TARGET_SUBXC.
	* config/sparc/sparc.md (seqdi<W:mode>_zero): Remove TARGET_SUBXC.
	(seqdi<W:mode>_zero_subxc): Delete.
	(neg_seqdi<W:mode>_zero): Remove TARGET_VIS3.
	(neg_seqdi<W:mode>_zero_vis3): Delete.
	(plus_seqdi<W:mode>_zero): Likewise.
	(minus_seqdi<W:mode>_zero): Likewise.
	(plus_plus_sltu<W:mode>): Accept only register.
	(addx<W:mode>): Likewise.
	(plus_sltu<W:mode>_vis3): Likewise.
	(plus_plus_sltu<W:mode>_vis3): Likewise.
	(neg_sgeu<W:mode>_vis3): Delete.
	(minus_sgeu<W:mode>_vis3): Likewise.
	(addxc<W:mode>): Accept only registers.
	(neg_sltu<W:mode>_subxc): Write %%g0 instead of 0.
	(minus_neg_sltu<W:mode>_subxc): Accept only register.
	(neg_plus_sltu<W:mode>_subxc): Likewise.
	(minus_sltu<W:mode>_subxc): Write %%g0 instead of 0.
	(minus_minus_sltu<W:mode>_subxc): Accept only register.
	(sgeu<W:mode>_insn_subxc): Delete.
	(plus_sgeu<W:mode>_subxc): Likewise.
	(subxc<W:mode>): Accept only register.
	(scc splitter): Split always GEU again.

From-SVN: r241012
This commit is contained in:
Eric Botcazou 2016-10-11 22:22:38 +00:00 • committed by Eric Botcazou
parent 0a4613f0c5
commit 4803de58c5
11 changed files with 128 additions and 244 deletions
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27
gcc/ChangeLog
View file

@ -1,3 +1,30 @@
2016-10-11 Eric Botcazou <ebotcazou@adacore.com>
* config/sparc/sparc.c (emit_scc_insn): Remove direct support for EQ
and GEU in DImode if TARGET_SUBXC.
* config/sparc/sparc.md (seqdi<W:mode>_zero): Remove TARGET_SUBXC.
(seqdi<W:mode>_zero_subxc): Delete.
(neg_seqdi<W:mode>_zero): Remove TARGET_VIS3.
(neg_seqdi<W:mode>_zero_vis3): Delete.
(plus_seqdi<W:mode>_zero): Likewise.
(minus_seqdi<W:mode>_zero): Likewise.
(plus_plus_sltu<W:mode>): Accept only register.
(addx<W:mode>): Likewise.
(plus_sltu<W:mode>_vis3): Likewise.
(plus_plus_sltu<W:mode>_vis3): Likewise.
(neg_sgeu<W:mode>_vis3): Delete.
(minus_sgeu<W:mode>_vis3): Likewise.
(addxc<W:mode>): Accept only registers.
(neg_sltu<W:mode>_subxc): Write %%g0 instead of 0.
(minus_neg_sltu<W:mode>_subxc): Accept only register.
(neg_plus_sltu<W:mode>_subxc): Likewise.
(minus_sltu<W:mode>_subxc): Write %%g0 instead of 0.
(minus_minus_sltu<W:mode>_subxc): Accept only register.
(sgeu<W:mode>_insn_subxc): Delete.
(plus_sgeu<W:mode>_subxc): Likewise.
(subxc<W:mode>): Accept only register.
(scc splitter): Split always GEU again.
2016-10-11 Jeff Law <law@redhat.com>
PR tree-optimization/77424

10
gcc/config/sparc/sparc.c
View file

@ -3023,10 +3023,8 @@ emit_scc_insn (rtx operands[])
gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
x, const0_rtx));
/* If we can use addx/subx or addxc/subxc, add a clobber for CC. */
if (mode == SImode
|| (code == NE && TARGET_VIS3)
|| (code == EQ && TARGET_SUBXC))
/* If we can use addx/subx or addxc, add a clobber for CC. */
if (mode == SImode || (code == NE && TARGET_VIS3))
{
rtx clobber
= gen_rtx_CLOBBER (VOIDmode,
@ -3039,12 +3037,10 @@ emit_scc_insn (rtx operands[])
return true;
}
/* We can do LTU in DImode using the addxc instruction with VIS3
and GEU in DImode using the subxc instruction with SUBXC. */
/* We can do LTU in DImode using the addxc instruction with VIS3. */
if (TARGET_ARCH64
&& mode == DImode
&& !((code == LTU || code == GTU) && TARGET_VIS3)
&& !((code == GEU || code == LEU) && TARGET_SUBXC)
&& gen_v9_scc (operands[0], code, x, y))
return true;

134
gcc/config/sparc/sparc.md
View file

@ -784,7 +784,7 @@
[(set (match_operand:W 0 "register_operand" "=&r")
(eq:W (match_operand:DI 1 "register_operand" "r")
(const_int 0)))]
"TARGET_ARCH64 && !TARGET_SUBXC"
"TARGET_ARCH64"
"#"
"&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
[(set (match_dup 0) (const_int 0))
@ -794,24 +794,11 @@
""
[(set_attr "length" "2")])
(define_insn_and_split "*seqdi<W:mode>_zero_subxc"
[(set (match_operand:W 0 "register_operand" "=r")
(eq:W (match_operand:DI 1 "register_operand" "r")
(const_int 0)))
(clobber (reg:CCX CC_REG))]
"TARGET_ARCH64 && TARGET_SUBXC"
"#"
""
[(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
(set (match_dup 0) (geu:W (reg:CCXC CC_REG) (const_int 0)))]
""
[(set_attr "length" "2")])
(define_insn_and_split "*neg_seqdi<W:mode>_zero"
[(set (match_operand:W 0 "register_operand" "=&r")
(neg:W (eq:W (match_operand:DI 1 "register_operand" "r")
(const_int 0))))]
"TARGET_ARCH64 && !TARGET_VIS3"
"TARGET_ARCH64"
"#"
"&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
[(set (match_dup 0) (const_int 0))
@ -821,19 +808,6 @@
""
[(set_attr "length" "2")])
(define_insn_and_split "*neg_seqdi<W:mode>_zero"
[(set (match_operand:W 0 "register_operand" "=r")
(neg:W (eq:W (match_operand:DI 1 "register_operand" "r")
(const_int 0))))
(clobber (reg:CCX CC_REG))]
"TARGET_ARCH64 && TARGET_VIS3"
"#"
""
[(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
(set (match_dup 0) (neg:W (geu:W (reg:CCXC CC_REG) (const_int 0))))]
""
[(set_attr "length" "2")])
;; We can also do (x + (i == 0)) and related, so put them in.
(define_insn_and_split "*plus_snesi<W:mode>_zero"
@ -935,8 +909,8 @@
(define_insn_and_split "*minus_snedi<W:mode>_zero"
[(set (match_operand:W 0 "register_operand" "=r")
(minus:W (match_operand:W 2 "register_operand" "r")
(ne:W (match_operand:DI 1 "register_operand" "r")
(const_int 0))))
(ne:W (match_operand:DI 1 "register_operand" "r")
(const_int 0))))
(clobber (reg:CCX CC_REG))]
"TARGET_ARCH64 && TARGET_SUBXC"
"#"
@ -979,21 +953,6 @@
""
[(set_attr "length" "2")])
(define_insn_and_split "*plus_seqdi<W:mode>_zero"
[(set (match_operand:W 0 "register_operand" "=r")
(plus:W (eq:W (match_operand:DI 1 "register_operand" "r")
(const_int 0))
(match_operand:W 2 "register_operand" "r")))
(clobber (reg:CCX CC_REG))]
"TARGET_ARCH64 && TARGET_SUBXC"
"#"
""
[(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
(set (match_dup 0) (plus:W (geu:W (reg:CCXC CC_REG) (const_int 0))
(match_dup 2)))]
""
[(set_attr "length" "2")])
(define_insn_and_split "*minus_seqsi<W:mode>_zero"
[(set (match_operand:W 0 "register_operand" "=r")
(minus:W (match_operand:W 2 "register_operand" "r")
@ -1009,21 +968,6 @@
""
[(set_attr "length" "2")])
(define_insn_and_split "*minus_seqdi<W:mode>_zero"
[(set (match_operand:W 0 "register_operand" "=r")
(minus:W (match_operand:W 2 "register_operand" "r")
(eq:W (match_operand:DI 1 "register_operand" "r")
(const_int 0))))
(clobber (reg:CCX CC_REG))]
"TARGET_ARCH64 && TARGET_VIS3"
"#"
""
[(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
(set (match_dup 0) (minus:W (match_dup 2)
(geu:W (reg:CCXC CC_REG) (const_int 0))))]
""
[(set_attr "length" "2")])
;; We can also do GEU and LTU directly, but these operate after a compare.
(define_insn "*sltu<W:mode>_insn"
@ -1046,7 +990,7 @@
[(set (match_operand:W 0 "register_operand" "=r")
(plus:W (plus:W (ltu:W (match_operand 3 "icc_register_operand" "X")
(const_int 0))
(match_operand:W 1 "arith_operand" "%r"))
(match_operand:W 1 "register_operand" "%r"))
(match_operand:W 2 "arith_operand" "rI")))]
"GET_MODE (operands[3]) == CCmode || GET_MODE (operands[3]) == CCCmode"
"addx\t%1, %2, %0"
@ -1080,7 +1024,7 @@
(define_insn "*addx<W:mode>"
[(set (match_operand:W 0 "register_operand" "=r")
(plus:W (plus:W (match_operand:W 1 "arith_operand" "%r")
(plus:W (plus:W (match_operand:W 1 "register_operand" "%r")
(match_operand:W 2 "arith_operand" "rI"))
(ltu:W (match_operand 3 "icc_register_operand" "X")
(const_int 0))))]
@ -1100,7 +1044,7 @@
[(set (match_operand:W 0 "register_operand" "=r")
(plus:W (ltu:W (match_operand 2 "icc_register_operand" "X")
(const_int 0))
(match_operand:W 1 "arith_operand" "rI")))]
(match_operand:W 1 "register_operand" "r")))]
"TARGET_ARCH64 && TARGET_VIS3
&& (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
"addxc\t%%g0, %1, %0"
@ -1110,41 +1054,22 @@
[(set (match_operand:W 0 "register_operand" "=r")
(plus:W (plus:W (ltu:W (match_operand 3 "icc_register_operand" "X")
(const_int 0))
(match_operand:W 1 "arith_operand" "%r"))
(match_operand:W 2 "arith_operand" "rI")))]
(match_operand:W 1 "register_operand" "%r"))
(match_operand:W 2 "register_operand" "r")))]
"TARGET_ARCH64 && TARGET_VIS3
&& (GET_MODE (operands[3]) == CCXmode || GET_MODE (operands[3]) == CCXCmode)"
"addxc\t%1, %2, %0"
[(set_attr "type" "ialuX")])
(define_insn "*neg_sgeu<W:mode>_vis3"
[(set (match_operand:W 0 "register_operand" "=r")
(neg:W (geu:W (match_operand 1 "icc_register_operand" "X")
(const_int 0))))]
"TARGET_ARCH64 && TARGET_VIS3
&& (GET_MODE (operands[1]) == CCXmode || GET_MODE (operands[1]) == CCXCmode)"
"addxc\t%%g0, -1, %0"
[(set_attr "type" "ialuX")])
(define_insn "*minus_sgeu<W:mode>_vis3"
[(set (match_operand:W 0 "register_operand" "=r")
(minus:W (match_operand:W 1 "register_operand" "r")
(geu:W (match_operand 2 "icc_register_operand" "X")
(const_int 0))))]
"TARGET_ARCH64 && TARGET_VIS3
&& (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
"addxc\t%1, -1, %0"
[(set_attr "type" "ialuX")])
(define_insn "*addxc<W:mode>"
[(set (match_operand:W 0 "register_operand" "=r")
(plus:W (plus:W (match_operand:W 1 "register_or_zero_operand" "%rJ")
(match_operand:W 2 "register_or_zero_operand" "rJ"))
(plus:W (plus:W (match_operand:W 1 "register_operand" "%r")
(match_operand:W 2 "register_operand" "r"))
(ltu:W (match_operand 3 "icc_register_operand" "X")
(const_int 0))))]
"TARGET_ARCH64 && TARGET_VIS3
&& (GET_MODE (operands[3]) == CCXmode || GET_MODE (operands[3]) == CCXCmode)"
"addxc\t%r1, %r2, %0"
"addxc\t%1, %2, %0"
[(set_attr "type" "ialuX")])
(define_insn "*neg_sltu<W:mode>"
@ -1233,14 +1158,14 @@
(const_int 0))))]
"TARGET_ARCH64 && TARGET_SUBXC
&& (GET_MODE (operands[1]) == CCXmode || GET_MODE (operands[1]) == CCXCmode)"
"subxc\t%%g0, 0, %0"
"subxc\t%%g0, %%g0, %0"
[(set_attr "type" "ialuX")])
(define_insn "*minus_neg_sltu<W:mode>_subxc"
[(set (match_operand:W 0 "register_operand" "=r")
(minus:W (neg:W (ltu:W (match_operand 2 "icc_register_operand" "X")
(const_int 0)))
(match_operand:W 1 "arith_operand" "rI")))]
(match_operand:W 1 "register_operand" "r")))]
"TARGET_ARCH64 && TARGET_SUBXC
&& (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
"subxc\t%%g0, %1, %0"
@ -1250,7 +1175,7 @@
[(set (match_operand:W 0 "register_operand" "=r")
(neg:W (plus:W (ltu:W (match_operand 2 "icc_register_operand" "X")
(const_int 0))
(match_operand:W 1 "arith_operand" "rI"))))]
(match_operand:W 1 "register_operand" "r"))))]
"TARGET_ARCH64 && TARGET_SUBXC
&& (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
"subxc\t%%g0, %1, %0"
@ -1263,7 +1188,7 @@
(const_int 0))))]
"TARGET_ARCH64 && TARGET_SUBXC
&& (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
"subxc\t%1, 0, %0"
"subxc\t%1, %%g0, %0"
[(set_attr "type" "ialuX")])
(define_insn "*minus_minus_sltu<W:mode>_subxc"
@ -1271,34 +1196,16 @@
(minus:W (minus:W (match_operand:W 1 "register_or_zero_operand" "rJ")
(ltu:W (match_operand 3 "icc_register_operand" "X")
(const_int 0)))
(match_operand:W 2 "arith_operand" "rI")))]
(match_operand:W 2 "register_operand" "r")))]
"TARGET_ARCH64 && TARGET_SUBXC
&& (GET_MODE (operands[3]) == CCXmode || GET_MODE (operands[3]) == CCXCmode)"
"subxc\t%r1, %2, %0"
[(set_attr "type" "ialuX")])
(define_insn "*sgeu<W:mode>_insn_subxc"
[(set (match_operand:W 0 "register_operand" "=r")
(geu:W (match_operand 1 "icc_register_operand" "X") (const_int 0)))]
"TARGET_ARCH64 && TARGET_SUBXC
&& (GET_MODE (operands[1]) == CCXmode || GET_MODE (operands[1]) == CCXCmode)"
"subxc\t%%g0, -1, %0"
[(set_attr "type" "ialuX")])
(define_insn "*plus_sgeu<W:mode>_subxc"
[(set (match_operand:W 0 "register_operand" "=r")
(plus:W (geu:W (match_operand 2 "icc_register_operand" "X")
(const_int 0))
(match_operand:W 1 "register_operand" "r")))]
"TARGET_ARCH64 && TARGET_SUBXC
&& (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
"subxc\t%1, -1, %0"
[(set_attr "type" "ialuX")])
(define_insn "*subxc<W:mode>"
[(set (match_operand:W 0 "register_operand" "=r")
(minus:W (minus:W (match_operand:W 1 "register_or_zero_operand" "rJ")
(match_operand:W 2 "arith_operand" "rI"))
(match_operand:W 2 "register_operand" "r"))
(ltu:W (match_operand 3 "icc_register_operand" "X")
(const_int 0))))]
"TARGET_ARCH64 && TARGET_SUBXC
@ -1316,11 +1223,6 @@
&& (GET_MODE (operands[2]) == CCXmode
|| GET_MODE (operands[2]) == CCXCmode)
&& TARGET_VIS3)
/* 64-bit GEU is better implemented using subxc with SUBXC. */
&& !(GET_CODE (operands[1]) == GEU
&& (GET_MODE (operands[2]) == CCXmode
|| GET_MODE (operands[2]) == CCXCmode)
&& TARGET_SUBXC)
/* 32-bit LTU/GEU are better implemented using addx/subx. */
&& !((GET_CODE (operands[1]) == LTU || GET_CODE (operands[1]) == GEU)
&& (GET_MODE (operands[2]) == CCmode

10
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,13 @@
2016-10-11 Eric Botcazou <ebotcazou@adacore.com>
* gcc.target/sparc/setcc-4.c: Adjust.
* gcc.target/sparc/setcc-5.c: Likewise.
* gcc.target/sparc/setcc-6.c: Likewise.
* gcc.target/sparc/setcc-7.c: Likewise.
* gcc.target/sparc/setcc-8.c: Likewise.
* gcc.target/sparc/setcc-9.c: Likewise.
* gcc.target/sparc/setcc-10.c: Delete.
2016-10-11 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/77942

23
gcc/testsuite/gcc.target/sparc/setcc-10.c
View file

@ -1,23 +0,0 @@
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
/* { dg-options "-O1 -msubxc" } */
long foo2 (long a, long i)
{
return a - (i != 0);
}
long foo4 (long a, long b, long i)
{
return a - b - (i != 0);
}
long foo5 (long a, long i)
{
return a + (i == 0);
}
/* { dg-final { scan-assembler-times "subxc\t%" 3 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 3 } } */
/* { dg-final { scan-assembler-not "add\t%" } } */
/* { dg-final { scan-assembler-not "sub\t%" } } */

37
gcc/testsuite/gcc.target/sparc/setcc-4.c
View file

@ -1,23 +1,44 @@
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
/* { dg-options "-O1 -msubxc" } */
/* { dg-options "-O1 -mno-vis3" } */
int eq (long a, long b)
long neq (long a, long b)
{
return a != b;
}
long eq (long a, long b)
{
return a == b;
}
int ge (unsigned long a, unsigned long b)
long lt (unsigned long a, unsigned long b)
{
return a >= b;
return a < b;
}
int le (unsigned long a, unsigned long b)
long leq (unsigned long a, unsigned long b)
{
return a <= b;
}
/* { dg-final { scan-assembler "xor\t%" } } */
/* { dg-final { scan-assembler-times "subxc\t%" 3 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 3 } } */
long geq (unsigned long a, unsigned long b)
{
return a >= b;
}
long gt (unsigned long a, unsigned long b)
{
return a > b;
}
/* { dg-final { scan-assembler-times "xor\t%" 2 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 4 } } */
/* { dg-final { scan-assembler-times "movrne\t%" 1 } } */
/* { dg-final { scan-assembler-times "movre\t%" 1 } } */
/* { dg-final { scan-assembler-times "movlu\t%" 1 } } */
/* { dg-final { scan-assembler-times "movleu\t%" 1 } } */
/* { dg-final { scan-assembler-times "movgeu\t%" 1 } } */
/* { dg-final { scan-assembler-times "movgu\t%" 1 } } */
/* { dg-final { scan-assembler-not "sra\t%" } } */
/* { dg-final { scan-assembler-not "and\t%" } } */

28
gcc/testsuite/gcc.target/sparc/setcc-5.c
View file

@ -1,44 +1,24 @@
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
/* { dg-options "-O1 -mno-vis3 -mno-subxc" } */
/* { dg-options "-O1 -mvis3" } */
long neq (long a, long b)
{
return a != b;
}
long eq (long a, long b)
{
return a == b;
}
long lt (unsigned long a, unsigned long b)
{
return a < b;
}
long leq (unsigned long a, unsigned long b)
{
return a <= b;
}
long geq (unsigned long a, unsigned long b)
{
return a >= b;
}
long gt (unsigned long a, unsigned long b)
{
return a > b;
}
/* { dg-final { scan-assembler-times "xor\t%" 2 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 4 } } */
/* { dg-final { scan-assembler-times "movrne\t%" 1 } } */
/* { dg-final { scan-assembler-times "movre\t%" 1 } } */
/* { dg-final { scan-assembler-times "movlu\t%" 1 } } */
/* { dg-final { scan-assembler-times "movleu\t%" 1 } } */
/* { dg-final { scan-assembler-times "movgeu\t%" 1 } } */
/* { dg-final { scan-assembler-times "movgu\t%" 1 } } */
/* { dg-final { scan-assembler-times "xor\t%" 1 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 3 } } */
/* { dg-final { scan-assembler-times "addxc\t%" 3 } } */
/* { dg-final { scan-assembler-not "sra\t%" } } */
/* { dg-final { scan-assembler-not "and\t%" } } */

36
gcc/testsuite/gcc.target/sparc/setcc-6.c
View file

@ -1,40 +1,38 @@
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
/* { dg-options "-O1 -mvis3 -msubxc" } */
/* { dg-options "-O1" } */
long neq (long a, long b)
int foo1 (int a, int i)
{
return a != b;
return a + (i != 0);
}
long eq (long a, long b)
int foo2 (int a, int i)
{
return a == b;
return a - (i != 0);
}
long lt (unsigned long a, unsigned long b)
int foo3 (int a, int b, int i)
{
return a < b;
return a + b + (i != 0);
}
long leq (unsigned long a, unsigned long b)
int foo4 (int a, int b, int i)
{
return a <= b;
return a - b - (i != 0);
}
long geq (unsigned long a, unsigned long b)
int foo5 (int a, int i)
{
return a >= b;
return a + (i == 0);
}
long gt (unsigned long a, unsigned long b)
int foo6 (int a, int i)
{
return a > b;
return a - (i == 0);
}
/* { dg-final { scan-assembler-times "xor\t%" 2 } } */
/* { dg-final { scan-assembler-times "addx\t%" 3 } } */
/* { dg-final { scan-assembler-times "subx\t%" 3 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 6 } } */
/* { dg-final { scan-assembler-times "addxc\t%" 3 } } */
/* { dg-final { scan-assembler-times "subxc\t%" 3 } } */
/* { dg-final { scan-assembler-not "sra\t%" } } */
/* { dg-final { scan-assembler-not "and\t%" } } */
/* { dg-final { scan-assembler-not "add\t%" } } */
/* { dg-final { scan-assembler-not "sub\t%" } } */

15
gcc/testsuite/gcc.target/sparc/setcc-7.c
View file

@ -1,32 +1,33 @@
/* { dg-do compile } */
/* { dg-options "-O1" } */
/* { dg-require-effective-target lp64 } */
/* { dg-options "-O1 -mno-vis3" } */
int foo1 (int a, int i)
long foo1 (long a, int i)
{
return a + (i != 0);
}
int foo2 (int a, int i)
long foo2 (long a, int i)
{
return a - (i != 0);
}
int foo3 (int a, int b, int i)
long foo3 (long a, long b, int i)
{
return a + b + (i != 0);
}
int foo4 (int a, int b, int i)
long foo4 (long a, long b, int i)
{
return a - b - (i != 0);
}
int foo5 (int a, int i)
long foo5 (long a, int i)
{
return a + (i == 0);
}
int foo6 (int a, int i)
long foo6 (long a, int i)
{
return a - (i == 0);
}

32
gcc/testsuite/gcc.target/sparc/setcc-8.c
View file

@ -1,39 +1,17 @@
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
/* { dg-options "-O1 -mno-vis3 -mno-subxc" } */
/* { dg-options "-O1 -mvis3" } */
long foo1 (long a, int i)
long foo1 (long a, long i)
{
return a + (i != 0);
}
long foo2 (long a, int i)
{
return a - (i != 0);
}
long foo3 (long a, long b, int i)
long foo3 (long a, long b, long i)
{
return a + b + (i != 0);
}
long foo4 (long a, long b, int i)
{
return a - b - (i != 0);
}
long foo5 (long a, int i)
{
return a + (i == 0);
}
long foo6 (long a, int i)
{
return a - (i == 0);
}
/* { dg-final { scan-assembler-times "addx\t%" 3 } } */
/* { dg-final { scan-assembler-times "subx\t%" 3 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 6 } } */
/* { dg-final { scan-assembler-times "addxc\t%" 2 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 2 } } */
/* { dg-final { scan-assembler-not "add\t%" } } */
/* { dg-final { scan-assembler-not "sub\t%" } } */

20
gcc/testsuite/gcc.target/sparc/setcc-9.c
View file

@ -1,23 +1,17 @@
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
/* { dg-options "-O1 -mvis3" } */
/* { dg-options "-O1 -msubxc" } */
long foo1 (long a, long i)
long foo2 (long a, long i)
{
return a + (i != 0);
return a - (i != 0);
}
long foo3 (long a, long b, long i)
long foo4 (long a, long b, long i)
{
return a + b + (i != 0);
return a - b - (i != 0);
}
long foo6 (long a, long i)
{
return a - (i == 0);
}
/* { dg-final { scan-assembler-times "addxc\t%" 3 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 3 } } */
/* { dg-final { scan-assembler-not "add\t%" } } */
/* { dg-final { scan-assembler-times "subxc\t%" 2 } } */
/* { dg-final { scan-assembler-times "cmp\t%" 2 } } */
/* { dg-final { scan-assembler-not "sub\t%" } } */