sparc.md (UNSPEC_ALIGNADDRL): New unspec.
* config/sparc/sparc.md (UNSPEC_ALIGNADDRL): New unspec. (aligneddrl<P:mode>_vis): New pattern. (edge8_vis, edge8l_vis, edge16_vis, edge16l_vis, edge32_vis, edge32l_vis): Adjust to take Pmode arguments, and return SImode. * config/sparc/sparc.c (sparc_vis_init_builtins): Handle new alignaddrl insn, and adjust edge operations for updated types. * config/sparc/visintrin.h: Likewise. * doc/extend.texi: Make typing in VIS documentation match reality. From-SVN: r179012
This commit is contained in:
David S. Miller
David S. Miller
parent
458692b00c
commit
47640f4069
5 changed files with 138 additions and 81 deletions
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@ -1,3 +1,14 @@
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2011-09-20 David S. Miller <davem@davemloft.net>
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* config/sparc/sparc.md (UNSPEC_ALIGNADDRL): New unspec.
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(aligneddrl<P:mode>_vis): New pattern.
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(edge8_vis, edge8l_vis, edge16_vis, edge16l_vis, edge32_vis,
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edge32l_vis): Adjust to take Pmode arguments, and return SImode.
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* config/sparc/sparc.c (sparc_vis_init_builtins): Handle new
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alignaddrl insn, and adjust edge operations for updated types.
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* config/sparc/visintrin.h: Likewise.
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* doc/extend.texi: Make typing in VIS documentation match reality.
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2011-09-20 Terry Guo <terry.guo@arm.com>
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* config/arm/arm-arches.def: Add armv6s-m.
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@ -9149,6 +9149,9 @@ sparc_vis_init_builtins (void)
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tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
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ptr_type_node,
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intDI_type_node, 0);
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tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node,
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ptr_type_node,
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ptr_type_node, 0);
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/* Packing and expanding vectors. */
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def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi);
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@ -9186,29 +9189,55 @@ sparc_vis_init_builtins (void)
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def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
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di_ftype_di_di);
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if (TARGET_ARCH64)
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def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
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ptr_ftype_ptr_di);
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{
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def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
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ptr_ftype_ptr_di);
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def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
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ptr_ftype_ptr_di);
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}
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else
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def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
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ptr_ftype_ptr_si);
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{
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def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
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ptr_ftype_ptr_si);
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def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis,
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ptr_ftype_ptr_si);
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}
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/* Pixel distance. */
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def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
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di_ftype_v8qi_v8qi_di);
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/* Edge handling. */
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def_builtin ("__builtin_vis_edge8", CODE_FOR_edge8_vis,
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di_ftype_di_di);
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def_builtin ("__builtin_vis_edge8l", CODE_FOR_edge8l_vis,
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di_ftype_di_di);
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def_builtin ("__builtin_vis_edge16", CODE_FOR_edge16_vis,
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di_ftype_di_di);
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def_builtin ("__builtin_vis_edge16l", CODE_FOR_edge16l_vis,
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di_ftype_di_di);
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def_builtin ("__builtin_vis_edge32", CODE_FOR_edge32_vis,
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di_ftype_di_di);
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def_builtin ("__builtin_vis_edge32l", CODE_FOR_edge32l_vis,
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di_ftype_di_di);
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if (TARGET_ARCH64)
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{
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def_builtin ("__builtin_vis_edge8", CODE_FOR_edge8di_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge16", CODE_FOR_edge16di_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge32", CODE_FOR_edge32di_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis,
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si_ftype_ptr_ptr);
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}
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else
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{
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def_builtin ("__builtin_vis_edge8", CODE_FOR_edge8si_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge16", CODE_FOR_edge16si_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge32", CODE_FOR_edge32si_vis,
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si_ftype_ptr_ptr);
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def_builtin ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis,
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si_ftype_ptr_ptr);
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}
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}
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/* Handle TARGET_EXPAND_BUILTIN target hook.
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@ -66,6 +66,7 @@
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(UNSPEC_EDGE16L 54)
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(UNSPEC_EDGE32 55)
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(UNSPEC_EDGE32L 56)
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(UNSPEC_ALIGNADDRL 57)
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(UNSPEC_SP_SET 60)
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(UNSPEC_SP_TEST 61)
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@ -7798,6 +7799,14 @@
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"TARGET_VIS"
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"alignaddr\t%r1, %r2, %0")
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(define_insn "alignaddrl<P:mode>_vis"
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[(set (match_operand:P 0 "register_operand" "=r")
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(unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
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(match_operand:P 2 "register_or_zero_operand" "rJ")]
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UNSPEC_ALIGNADDRL))]
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"TARGET_VIS"
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"alignaddrl\t%r1, %r2, %0")
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(define_insn "pdist_vis"
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[(set (match_operand:DI 0 "register_operand" "=e")
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(unspec:DI [(match_operand:V8QI 1 "register_operand" "e")
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@ -7811,68 +7820,68 @@
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;; Edge instructions produce condition codes equivalent to a 'subcc'
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;; with the same operands.
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(define_insn "edge8_vis"
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[(set (reg:CCX_NOOV 100)
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(compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
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(match_operand:DI 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8))]
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(define_insn "edge8<P:mode>_vis"
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[(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
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(match_operand:P 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8))]
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"TARGET_VIS"
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"edge8\t%r1, %r2, %0"
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[(set_attr "type" "edge")])
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(define_insn "edge8l_vis"
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[(set (reg:CCX_NOOV 100)
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(compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
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(match_operand:DI 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8L))]
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(define_insn "edge8l<P:mode>_vis"
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[(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
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(match_operand:P 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8L))]
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"TARGET_VIS"
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"edge8l\t%r1, %r2, %0"
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[(set_attr "type" "edge")])
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(define_insn "edge16_vis"
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[(set (reg:CCX_NOOV 100)
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(compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
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(match_operand:DI 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16))]
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(define_insn "edge16<P:mode>_vis"
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[(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
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(match_operand:P 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16))]
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"TARGET_VIS"
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"edge16\t%r1, %r2, %0"
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[(set_attr "type" "edge")])
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(define_insn "edge16l_vis"
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[(set (reg:CCX_NOOV 100)
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(compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
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(match_operand:DI 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16L))]
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(define_insn "edge16l<P:mode>_vis"
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[(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
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(match_operand:P 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16L))]
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"TARGET_VIS"
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"edge16l\t%r1, %r2, %0"
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[(set_attr "type" "edge")])
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(define_insn "edge32_vis"
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[(set (reg:CCX_NOOV 100)
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(compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
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(match_operand:DI 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32))]
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(define_insn "edge32<P:mode>_vis"
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[(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
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(match_operand:P 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32))]
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"TARGET_VIS"
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"edge32\t%r1, %r2, %0"
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[(set_attr "type" "edge")])
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(define_insn "edge32l_vis"
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[(set (reg:CCX_NOOV 100)
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(compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "rJ")
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(match_operand:DI 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32L))]
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(define_insn "edge32l<P:mode>_vis"
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[(set (reg:CC_NOOV 100)
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(compare:CC_NOOV (minus:P (match_operand:P 1 "register_operand" "rJ")
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(match_operand:P 2 "register_operand" "rJ"))
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32L))]
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"TARGET_VIS"
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"edge32l\t%r1, %r2, %0"
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[(set_attr "type" "edge")])
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@ -38,6 +38,13 @@ __vis_alignaddr (void *__A, long __B)
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return __builtin_vis_alignaddr (__A, __B);
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}
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extern __inline void *
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_alignaddrl (void *__A, long __B)
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{
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return __builtin_vis_alignaddrl (__A, __B);
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}
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extern __inline __i64
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_faligndatadi (__i64 __A, __i64 __B)
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@ -157,44 +164,44 @@ __vis_pdist (__v8qi __A, __v8qi __B, __i64 __C)
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return __builtin_vis_pdist (__A, __B, __C);
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}
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extern __inline __i64
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_edge8 (__i64 __A, __i64 __B)
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__vis_edge8 (void *__A, void *__B)
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{
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return __builtin_vis_edge8 (__A, __B);
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}
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extern __inline __i64
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_edge8l (__i64 __A, __i64 __B)
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__vis_edge8l (void *__A, void *__B)
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{
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return __builtin_vis_edge8l (__A, __B);
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}
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extern __inline __i64
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_edge16 (__i64 __A, __i64 __B)
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__vis_edge16 (void *__A, void *__B)
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{
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return __builtin_vis_edge16 (__A, __B);
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}
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extern __inline __i64
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_edge16l (__i64 __A, __i64 __B)
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__vis_edge16l (void *__A, void *__B)
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{
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return __builtin_vis_edge16l (__A, __B);
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}
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extern __inline __i64
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_edge32 (__i64 __A, __i64 __B)
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__vis_edge32 (void *__A, void *__B)
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{
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return __builtin_vis_edge32 (__A, __B);
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}
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extern __inline __i64
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extern __inline int
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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__vis_edge32l (__i64 __A, __i64 __B)
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__vis_edge32l (void *__A, void *__B)
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{
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return __builtin_vis_edge32l (__A, __B);
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}
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@ -12932,10 +12932,11 @@ switch, the VIS extension is exposed as the following built-in functions:
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typedef int v2si __attribute__ ((vector_size (8)));
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typedef short v4hi __attribute__ ((vector_size (8)));
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typedef short v2hi __attribute__ ((vector_size (4)));
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typedef char v8qi __attribute__ ((vector_size (8)));
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typedef char v4qi __attribute__ ((vector_size (4)));
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typedef unsigned char v8qi __attribute__ ((vector_size (8)));
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typedef unsigned char v4qi __attribute__ ((vector_size (4)));
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void * __builtin_vis_alignaddr (void *, long);
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void * __builtin_vis_alignaddrl (void *, long);
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int64_t __builtin_vis_faligndatadi (int64_t, int64_t);
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v2si __builtin_vis_faligndatav2si (v2si, v2si);
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v4hi __builtin_vis_faligndatav4hi (v4si, v4si);
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@ -12944,26 +12945,26 @@ v8qi __builtin_vis_faligndatav8qi (v8qi, v8qi);
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v4hi __builtin_vis_fexpand (v4qi);
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v4hi __builtin_vis_fmul8x16 (v4qi, v4hi);
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v4hi __builtin_vis_fmul8x16au (v4qi, v4hi);
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v4hi __builtin_vis_fmul8x16al (v4qi, v4hi);
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v4hi __builtin_vis_fmul8x16au (v4qi, v2hi);
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v4hi __builtin_vis_fmul8x16al (v4qi, v2hi);
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v4hi __builtin_vis_fmul8sux16 (v8qi, v4hi);
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v4hi __builtin_vis_fmul8ulx16 (v8qi, v4hi);
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v2si __builtin_vis_fmuld8sux16 (v4qi, v2hi);
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v2si __builtin_vis_fmuld8ulx16 (v4qi, v2hi);
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v4qi __builtin_vis_fpack16 (v4hi);
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v8qi __builtin_vis_fpack32 (v2si, v2si);
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v8qi __builtin_vis_fpack32 (v2si, v8qi);
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v2hi __builtin_vis_fpackfix (v2si);
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v8qi __builtin_vis_fpmerge (v4qi, v4qi);
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int64_t __builtin_vis_pdist (v8qi, v8qi, int64_t);
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int64_t __builtin_vis_edge8 (int64_t, int64_t);
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int64_t __builtin_vis_edge8l (int64_t, int64_t);
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int64_t __builtin_vis_edge16 (int64_t, int64_t);
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int64_t __builtin_vis_edge16l (int64_t, int64_t);
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int64_t __builtin_vis_edge32 (int64_t, int64_t);
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int64_t __builtin_vis_edge32l (int64_t, int64_t);
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int __builtin_vis_edge8 (void *, void *);
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int __builtin_vis_edge8l (void *, void *);
|
||||
int __builtin_vis_edge16 (void *, void *);
|
||||
int __builtin_vis_edge16l (void *, void *);
|
||||
int __builtin_vis_edge32 (void *, void *);
|
||||
int __builtin_vis_edge32l (void *, void *);
|
||||
@end smallexample
|
||||
|
||||
@node SPU Built-in Functions
|
||||
|
|
|
|||
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Add table
Reference in a new issue