aarch64-simd.md (aarch64_ld1x2<VQ:mode>): New.
gcc/ChangeLog: 2017-12-27 Kugan Vivekanandarajah <kuganv@linaro.org> * config/aarch64/aarch64-simd.md (aarch64_ld1x2<VQ:mode>): New. (aarch64_ld1x2<VDC:mode>): Likewise. (aarch64_simd_ld1<mode>_x2): Likewise. (aarch64_simd_ld1<mode>_x2): Likewise. * config/aarch64/arm_neon.h (vld1_u8_x2): New. (vld1_s8_x2): Likewise. (vld1_u16_x2): Likewise. (vld1_s16_x2): Likewise. (vld1_u32_x2): Likewise. (vld1_s32_x2): Likewise. (vld1_u64_x2): Likewise. (vld1_s64_x2): Likewise. (vld1_f16_x2): Likewise. (vld1_f32_x2): Likewise. (vld1_f64_x2): Likewise. (vld1_p8_x2): Likewise. (vld1_p16_x2): Likewise. (vld1_p64_x2): Likewise. (vld1q_u8_x2): Likewise. (vld1q_s8_x2): Likewise. (vld1q_u16_x2): Likewise. (vld1q_s16_x2): Likewise. (vld1q_u32_x2): Likewise. (vld1q_s32_x2): Likewise. (vld1q_u64_x2): Likewise. (vld1q_s64_x2): Likewise. (vld1q_f16_x2): Likewise. (vld1q_f32_x2): Likewise. (vld1q_f64_x2): Likewise. (vld1q_p8_x2): Likewise. (vld1q_p16_x2): Likewise. (vld1q_p64_x2): Likewise. gcc/testsuite/ChangeLog: 2017-12-27 Kugan Vivekanandarajah <kuganv@linaro.org> * gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: New test. From-SVN: r256010
This commit is contained in:
Kugan Vivekanandarajah
Kugan Vivekanandarajah
parent
96863f32b5
commit
467e6f1bb1
6 changed files with 499 additions and 1 deletions
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@ -1,3 +1,38 @@
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2017-12-27 Kugan Vivekanandarajah <kuganv@linaro.org>
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* config/aarch64/aarch64-simd.md (aarch64_ld1x2<VQ:mode>): New.
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(aarch64_ld1x2<VDC:mode>): Likewise.
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(aarch64_simd_ld1<mode>_x2): Likewise.
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(aarch64_simd_ld1<mode>_x2): Likewise.
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* config/aarch64/arm_neon.h (vld1_u8_x2): New.
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(vld1_s8_x2): Likewise.
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(vld1_u16_x2): Likewise.
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(vld1_s16_x2): Likewise.
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(vld1_u32_x2): Likewise.
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(vld1_s32_x2): Likewise.
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(vld1_u64_x2): Likewise.
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(vld1_s64_x2): Likewise.
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(vld1_f16_x2): Likewise.
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(vld1_f32_x2): Likewise.
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(vld1_f64_x2): Likewise.
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(vld1_p8_x2): Likewise.
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(vld1_p16_x2): Likewise.
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(vld1_p64_x2): Likewise.
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(vld1q_u8_x2): Likewise.
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(vld1q_s8_x2): Likewise.
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(vld1q_u16_x2): Likewise.
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(vld1q_s16_x2): Likewise.
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(vld1q_u32_x2): Likewise.
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(vld1q_s32_x2): Likewise.
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(vld1q_u64_x2): Likewise.
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(vld1q_s64_x2): Likewise.
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(vld1q_f16_x2): Likewise.
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(vld1q_f32_x2): Likewise.
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(vld1q_f64_x2): Likewise.
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(vld1q_p8_x2): Likewise.
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(vld1q_p16_x2): Likewise.
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(vld1q_p64_x2): Likewise.
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2017-12-27 Martin Liska <mliska@suse.cz>
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PR tree-optimization/83552
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@ -86,6 +86,10 @@
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VAR1 (SETREGP, set_qregoi, 0, v2di)
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VAR1 (SETREGP, set_qregci, 0, v2di)
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VAR1 (SETREGP, set_qregxi, 0, v2di)
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/* Implemented by aarch64_ld1x2<VQ:mode>. */
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BUILTIN_VQ (LOADSTRUCT, ld1x2, 0)
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/* Implemented by aarch64_ld1x2<VDC:mode>. */
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BUILTIN_VDC (LOADSTRUCT, ld1x2, 0)
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/* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */
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BUILTIN_VDC (LOADSTRUCT, ld2, 0)
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BUILTIN_VDC (LOADSTRUCT, ld3, 0)
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@ -571,4 +575,4 @@
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BUILTIN_GPI (UNOP, fix_truncdf, 2)
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BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2)
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BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2)
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BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
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BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)
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@ -5296,6 +5296,33 @@
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DONE;
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})
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(define_expand "aarch64_ld1x2<VQ:mode>"
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[(match_operand:OI 0 "register_operand" "=w")
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(match_operand:DI 1 "register_operand" "r")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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"TARGET_SIMD"
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{
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machine_mode mode = OImode;
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rtx mem = gen_rtx_MEM (mode, operands[1]);
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emit_insn (gen_aarch64_simd_ld1<VQ:mode>_x2 (operands[0], mem));
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DONE;
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})
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(define_expand "aarch64_ld1x2<VDC:mode>"
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[(match_operand:OI 0 "register_operand" "=w")
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(match_operand:DI 1 "register_operand" "r")
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(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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"TARGET_SIMD"
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{
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machine_mode mode = OImode;
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rtx mem = gen_rtx_MEM (mode, operands[1]);
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emit_insn (gen_aarch64_simd_ld1<VDC:mode>_x2 (operands[0], mem));
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DONE;
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})
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(define_expand "aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>"
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[(match_operand:VSTRUCT 0 "register_operand" "=w")
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(match_operand:DI 1 "register_operand" "w")
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@ -5692,6 +5719,27 @@
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[(set_attr "type" "neon_load1_all_lanes")]
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)
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(define_insn "aarch64_simd_ld1<mode>_x2"
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[(set (match_operand:OI 0 "register_operand" "=w")
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(unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")
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(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_LD1))]
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"TARGET_SIMD"
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"ld1\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
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[(set_attr "type" "neon_load1_2reg<q>")]
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)
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(define_insn "aarch64_simd_ld1<mode>_x2"
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[(set (match_operand:OI 0 "register_operand" "=w")
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(unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")
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(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_LD1))]
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"TARGET_SIMD"
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"ld1\\t{%S0.<Vtype> - %T0.<Vtype>}, %1"
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[(set_attr "type" "neon_load1_2reg<q>")]
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)
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(define_insn "aarch64_frecpe<mode>"
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[(set (match_operand:VHSDF 0 "register_operand" "=w")
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(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")]
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@ -17228,6 +17228,342 @@ vld1q_u8 (const uint8_t *a)
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__builtin_aarch64_ld1v16qi ((const __builtin_aarch64_simd_qi *) a);
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}
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__extension__ extern __inline uint8x8x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_u8_x2 (const uint8_t *__a)
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{
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uint8x8x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v8qi ((const __builtin_aarch64_simd_qi *) __a);
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ret.val[0] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
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ret.val[1] = (uint8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
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return ret;
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}
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__extension__ extern __inline int8x8x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_s8_x2 (const int8_t *__a)
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{
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int8x8x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v8qi ((const __builtin_aarch64_simd_qi *) __a);
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ret.val[0] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
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ret.val[1] = (int8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
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return ret;
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}
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__extension__ extern __inline uint16x4x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_u16_x2 (const uint16_t *__a)
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{
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uint16x4x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v4hi ((const __builtin_aarch64_simd_hi *) __a);
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ret.val[0] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
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ret.val[1] = (uint16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
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return ret;
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}
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__extension__ extern __inline int16x4x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_s16_x2 (const int16_t *__a)
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{
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int16x4x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v4hi ((const __builtin_aarch64_simd_hi *) __a);
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ret.val[0] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
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ret.val[1] = (int16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
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return ret;
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}
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__extension__ extern __inline uint32x2x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_u32_x2 (const uint32_t *__a)
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{
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uint32x2x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v2si ((const __builtin_aarch64_simd_si *) __a);
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ret.val[0] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
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ret.val[1] = (uint32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
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return ret;
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}
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__extension__ extern __inline int32x2x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_s32_x2 (const int32_t *__a)
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{
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int32x2x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v2si ((const __builtin_aarch64_simd_si *) __a);
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ret.val[0] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 0);
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ret.val[1] = (int32x2_t) __builtin_aarch64_get_dregoiv2si (__o, 1);
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return ret;
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}
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__extension__ extern __inline uint64x1x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_u64_x2 (const uint64_t *__a)
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{
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uint64x1x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2di ((const __builtin_aarch64_simd_di *) __a);
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ret.val[0] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
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ret.val[1] = (uint64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
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return ret;
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}
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__extension__ extern __inline int64x1x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_s64_x2 (const int64_t *__a)
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{
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int64x1x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2di ((const __builtin_aarch64_simd_di *) __a);
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ret.val[0] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
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ret.val[1] = (int64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
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return ret;
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}
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__extension__ extern __inline float16x4x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_f16_x2 (const float16_t *__a)
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{
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float16x4x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v4hf ((const __builtin_aarch64_simd_hf *) __a);
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ret.val[0] = (float16x4_t) __builtin_aarch64_get_dregoiv4hf (__o, 0);
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ret.val[1] = (float16x4_t) __builtin_aarch64_get_dregoiv4hf (__o, 1);
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return ret;
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}
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__extension__ extern __inline float32x2x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_f32_x2 (const float32_t *__a)
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{
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float32x2x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v2sf ((const __builtin_aarch64_simd_sf *) __a);
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ret.val[0] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 0);
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ret.val[1] = (float32x2_t) __builtin_aarch64_get_dregoiv2sf (__o, 1);
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return ret;
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}
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__extension__ extern __inline float64x1x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_f64_x2 (const float64_t *__a)
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{
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float64x1x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2df ((const __builtin_aarch64_simd_df *) __a);
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ret.val[0] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 0)};
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ret.val[1] = (float64x1_t) {__builtin_aarch64_get_dregoidf (__o, 1)};
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return ret;
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}
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__extension__ extern __inline poly8x8x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_p8_x2 (const poly8_t *__a)
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{
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poly8x8x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v8qi ((const __builtin_aarch64_simd_qi *) __a);
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ret.val[0] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 0);
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ret.val[1] = (poly8x8_t) __builtin_aarch64_get_dregoiv8qi (__o, 1);
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return ret;
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}
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__extension__ extern __inline poly16x4x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_p16_x2 (const poly16_t *__a)
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{
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poly16x4x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v4hi ((const __builtin_aarch64_simd_hi *) __a);
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ret.val[0] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 0);
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ret.val[1] = (poly16x4_t) __builtin_aarch64_get_dregoiv4hi (__o, 1);
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return ret;
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}
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__extension__ extern __inline poly64x1x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1_p64_x2 (const poly64_t *__a)
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{
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poly64x1x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2di ((const __builtin_aarch64_simd_di *) __a);
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ret.val[0] = (poly64x1_t) __builtin_aarch64_get_dregoidi (__o, 0);
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ret.val[1] = (poly64x1_t) __builtin_aarch64_get_dregoidi (__o, 1);
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return ret;
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}
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__extension__ extern __inline uint8x16x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1q_u8_x2 (const uint8_t *__a)
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{
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uint8x16x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v16qi ((const __builtin_aarch64_simd_qi *) __a);
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ret.val[0] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
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ret.val[1] = (uint8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
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return ret;
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}
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__extension__ extern __inline int8x16x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld1q_s8_x2 (const int8_t *__a)
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{
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int8x16x2_t ret;
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__builtin_aarch64_simd_oi __o;
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__o = __builtin_aarch64_ld1x2v16qi ((const __builtin_aarch64_simd_qi *) __a);
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ret.val[0] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
|
||||
ret.val[1] = (int8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline uint16x8x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_u16_x2 (const uint16_t *__a)
|
||||
{
|
||||
uint16x8x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v8hi ((const __builtin_aarch64_simd_hi *) __a);
|
||||
ret.val[0] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
|
||||
ret.val[1] = (uint16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline int16x8x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_s16_x2 (const int16_t *__a)
|
||||
{
|
||||
int16x8x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v8hi ((const __builtin_aarch64_simd_hi *) __a);
|
||||
ret.val[0] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
|
||||
ret.val[1] = (int16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline uint32x4x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_u32_x2 (const uint32_t *__a)
|
||||
{
|
||||
uint32x4x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v4si ((const __builtin_aarch64_simd_si *) __a);
|
||||
ret.val[0] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
|
||||
ret.val[1] = (uint32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline int32x4x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_s32_x2 (const int32_t *__a)
|
||||
{
|
||||
int32x4x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v4si ((const __builtin_aarch64_simd_si *) __a);
|
||||
ret.val[0] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 0);
|
||||
ret.val[1] = (int32x4_t) __builtin_aarch64_get_qregoiv4si (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline uint64x2x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_u64_x2 (const uint64_t *__a)
|
||||
{
|
||||
uint64x2x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v2di ((const __builtin_aarch64_simd_di *) __a);
|
||||
ret.val[0] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
|
||||
ret.val[1] = (uint64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline int64x2x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_s64_x2 (const int64_t *__a)
|
||||
{
|
||||
int64x2x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v2di ((const __builtin_aarch64_simd_di *) __a);
|
||||
ret.val[0] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
|
||||
ret.val[1] = (int64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline float16x8x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_f16_x2 (const float16_t *__a)
|
||||
{
|
||||
float16x8x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v8hf ((const __builtin_aarch64_simd_hf *) __a);
|
||||
ret.val[0] = (float16x8_t) __builtin_aarch64_get_qregoiv8hf (__o, 0);
|
||||
ret.val[1] = (float16x8_t) __builtin_aarch64_get_qregoiv8hf (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline float32x4x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_f32_x2 (const float32_t *__a)
|
||||
{
|
||||
float32x4x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v4sf ((const __builtin_aarch64_simd_sf *) __a);
|
||||
ret.val[0] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 0);
|
||||
ret.val[1] = (float32x4_t) __builtin_aarch64_get_qregoiv4sf (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline float64x2x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_f64_x2 (const float64_t *__a)
|
||||
{
|
||||
float64x2x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v2df ((const __builtin_aarch64_simd_df *) __a);
|
||||
ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 0);
|
||||
ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregoiv2df (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline poly8x16x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_p8_x2 (const poly8_t *__a)
|
||||
{
|
||||
poly8x16x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v16qi ((const __builtin_aarch64_simd_qi *) __a);
|
||||
ret.val[0] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 0);
|
||||
ret.val[1] = (poly8x16_t) __builtin_aarch64_get_qregoiv16qi (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline poly16x8x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_p16_x2 (const poly16_t *__a)
|
||||
{
|
||||
poly16x8x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v8hi ((const __builtin_aarch64_simd_hi *) __a);
|
||||
ret.val[0] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 0);
|
||||
ret.val[1] = (poly16x8_t) __builtin_aarch64_get_qregoiv8hi (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline poly64x2x2_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_p64_x2 (const poly64_t *__a)
|
||||
{
|
||||
poly64x2x2_t ret;
|
||||
__builtin_aarch64_simd_oi __o;
|
||||
__o = __builtin_aarch64_ld1x2v2di ((const __builtin_aarch64_simd_di *) __a);
|
||||
ret.val[0] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 0);
|
||||
ret.val[1] = (poly64x2_t) __builtin_aarch64_get_qregoiv2di (__o, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
__extension__ extern __inline uint16x8_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
vld1q_u16 (const uint16_t *a)
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2017-12-27 Kugan Vivekanandarajah <kuganv@linaro.org>
|
||||
|
||||
* gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: New test.
|
||||
|
||||
2017-12-27 Martin Liska <mliska@suse.cz>
|
||||
|
||||
PR tree-optimization/83552
|
||||
|
|
|
|||
71
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
Normal file
71
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-O3" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
#define TESTMETH(BASE, ELTS, SUFFIX) \
|
||||
int __attribute__ ((noinline)) \
|
||||
test_vld##SUFFIX##_x2 () \
|
||||
{ \
|
||||
BASE##_t data[ELTS * 2]; \
|
||||
BASE##_t temp[ELTS * 2]; \
|
||||
BASE##x##ELTS##x##2##_t vectors; \
|
||||
int i,j; \
|
||||
for (i = 0; i < ELTS * 2; i++) \
|
||||
data [i] = (BASE##_t) 2*i + 1; \
|
||||
asm volatile ("" : : : "memory"); \
|
||||
vectors = vld1##SUFFIX##_x2 (data); \
|
||||
vst1##SUFFIX (temp, vectors.val[0]); \
|
||||
vst1##SUFFIX (&temp[ELTS], vectors.val[1]); \
|
||||
asm volatile ("" : : : "memory"); \
|
||||
for (j = 0; j < ELTS * 2; j++) \
|
||||
if (temp[j] != data[j]) \
|
||||
return 1; \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
#define VARIANTS(VARIANT) \
|
||||
VARIANT (uint8, 8, _u8) \
|
||||
VARIANT (uint16, 4, _u16) \
|
||||
VARIANT (uint32, 2, _u32) \
|
||||
VARIANT (uint64, 1, _u64) \
|
||||
VARIANT (int8, 8, _s8) \
|
||||
VARIANT (int16, 4, _s16) \
|
||||
VARIANT (int32, 2, _s32) \
|
||||
VARIANT (int64, 1, _s64) \
|
||||
VARIANT (poly8, 8, _p8) \
|
||||
VARIANT (poly16, 4, _p16) \
|
||||
VARIANT (float16, 4, _f16) \
|
||||
VARIANT (float32, 2, _f32) \
|
||||
VARIANT (float64, 1, _f64) \
|
||||
VARIANT (uint8, 16, q_u8) \
|
||||
VARIANT (uint16, 8, q_u16) \
|
||||
VARIANT (uint32, 4, q_u32) \
|
||||
VARIANT (uint64, 2, q_u64) \
|
||||
VARIANT (int8, 16, q_s8) \
|
||||
VARIANT (int16, 8, q_s16) \
|
||||
VARIANT (int32, 4, q_s32) \
|
||||
VARIANT (int64, 2, q_s64) \
|
||||
VARIANT (poly8, 16, q_p8) \
|
||||
VARIANT (poly16, 8, q_p16) \
|
||||
VARIANT (float16, 8, q_f16) \
|
||||
VARIANT (float32, 4, q_f32) \
|
||||
VARIANT (float64, 2, q_f64)
|
||||
|
||||
/* Tests of vld1_x2 and vld1q_x2. */
|
||||
VARIANTS (TESTMETH)
|
||||
|
||||
#define CHECK(BASE, ELTS, SUFFIX) \
|
||||
if (test_vld##SUFFIX##_x2 () != 0) \
|
||||
abort ();
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
VARIANTS (CHECK)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Add table
Reference in a new issue