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re PR testsuite/32014 (new gcc failures)

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PR testsuite/32014
        * config/rs6000/altivec.md (UNSPEC_VUPKHS_V4SF, UNSPEC_VUPKLS_V4SF):
        (UNSPEC_VUPKHU_V4SF, UNSPEC_VUPKLU_V4SF): New.
        (vec_unpacks_float_hi_v8hi, vec_unpacks_float_lo_v8hi): New patterns.
        (vec_unpacku_float_hi_v8hi, vec_unpacku_float_lo_v8hi): New patterns.

From-SVN: r126361
This commit is contained in:
Dorit Nuzman 2007-07-05 10:56:04 +00:00 • committed by Dorit Nuzman
parent b301e9b3a4
commit 4643b71608
2 changed files with 68 additions and 0 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2007-07-05 Dorit Nuzman <dorit@il.ibm.com>
PR testsuite/32014
* config/rs6000/altivec.md (UNSPEC_VUPKHS_V4SF, UNSPEC_VUPKLS_V4SF):
(UNSPEC_VUPKHU_V4SF, UNSPEC_VUPKLU_V4SF): New.
(vec_unpacks_float_hi_v8hi, vec_unpacks_float_lo_v8hi): New patterns.
(vec_unpacku_float_hi_v8hi, vec_unpacku_float_lo_v8hi): New patterns.
2007-07-05 Zdenek Dvorak <dvorakz@suse.cz>
* config/i386/i386.c (ix86_address_cost): Do not consider more complex

60
gcc/config/rs6000/altivec.md
View file

@ -147,6 +147,10 @@
(UNSPEC_VPERMHI 321)
(UNSPEC_INTERHI 322)
(UNSPEC_INTERLO 323)
(UNSPEC_VUPKHS_V4SF 324)
(UNSPEC_VUPKLS_V4SF 325)
(UNSPEC_VUPKHU_V4SF 326)
(UNSPEC_VUPKLU_V4SF 327)
])
(define_constants
@ -2933,3 +2937,59 @@
emit_insn (gen_altivec_vmrgl<VI_char> (operands[0], operands[1], operands[2]));
DONE;
}")
(define_expand "vec_unpacks_float_hi_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKHS_V4SF))]
"TARGET_ALTIVEC"
"
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
}")
(define_expand "vec_unpacks_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKLS_V4SF))]
"TARGET_ALTIVEC"
"
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
}")
(define_expand "vec_unpacku_float_hi_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKHU_V4SF))]
"TARGET_ALTIVEC"
"
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
}")
(define_expand "vec_unpacku_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKLU_V4SF))]
"TARGET_ALTIVEC"
"
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
}")