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[AArch64] Implement ADD in vector registers for 32-bit scalar values.

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gcc/

	* config/aarch64/aarch64.md (*addsi3_aarch64): Add alternative in
	vector registers.

gcc/testsuite/

	* gcc.target/aarch64/scalar_shift_1.c: Fix expected assembler.

From-SVN: r211887
This commit is contained in:
James Greenhalgh 2014-06-23 09:04:40 +00:00 • committed by James Greenhalgh
parent 1cff83e21d
commit 463036be82
4 changed files with 14 additions and 6 deletions
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5
gcc/ChangeLog
View file

@ -1,3 +1,8 @@
2014-06-23 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md (*addsi3_aarch64): Add alternative in
vector registers.
2014-06-23 Jan Hubicka <hubicka@ucw.cz>
* lto-cgraph.c (lto_output_node, input_node): Set/get init/fini priority

9
gcc/config/aarch64/aarch64.md
View file

@ -1157,16 +1157,17 @@
(define_insn "*addsi3_aarch64"
[(set
(match_operand:SI 0 "register_operand" "=rk,rk,rk")
(match_operand:SI 0 "register_operand" "=rk,rk,w,rk")
(plus:SI
(match_operand:SI 1 "register_operand" "%rk,rk,rk")
(match_operand:SI 2 "aarch64_plus_operand" "I,r,J")))]
(match_operand:SI 1 "register_operand" "%rk,rk,w,rk")
(match_operand:SI 2 "aarch64_plus_operand" "I,r,w,J")))]
""
"@
add\\t%w0, %w1, %2
add\\t%w0, %w1, %w2
add\\t%0.2s, %1.2s, %2.2s
sub\\t%w0, %w1, #%n2"
[(set_attr "type" "alu_imm,alu_reg,alu_imm")]
[(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")]
)
;; zero_extend version of above

4
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,7 @@
2014-06-23 James Greenhalgh <james.greenhalgh@arm.com>
* gcc.target/aarch64/scalar_shift_1.c: Fix expected assembler.
2014-06-20 Jan Hubicka <hubicka@ucw.cz>
* gcc.dg/localalias.c: Fix broken commit.

2
gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
View file

@ -193,7 +193,6 @@ test_corners_sisd_di (Int64x1 b)
return b;
}
/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 63" } } */
/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 1" } } */
Int32x1
test_corners_sisd_si (Int32x1 b)
@ -207,7 +206,6 @@ test_corners_sisd_si (Int32x1 b)
return b;
}
/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 31" } } */
/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 1" } } */