neon-schedgen.ml (core): New type.
2010-09-01 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/neon-schedgen.ml (core): New type. (allCores): List of supported cores. (availability_table): Add supported cores. (collate_bypasses): Accept core as a parameter. (worst_case_latencies_and_bypasses): Accept core as a parameter. (emit_insn_reservations): Accept core as a parameter. Use tuneStr and coreStr to get tune attribute and prefix for functional units. (emit_bypasses): Accept core name and use it. (calculate_per_core_availability_table): New. (filter_core): New. (calculate_core_availability_table): New. (main): Use calculate_core_availablity_table. * config/arm/cortex-a8-neon.md: Update copyright year. Regenerated from ml file and merged in. (neon_mrrc, neon_mrc): Rename to cortex_a8_neon_mrrc and cortex_a8_neon_mrc. From-SVN: r163737
This commit is contained in:
Ramana Radhakrishnan
Ramana Radhakrishnan
parent
f685731072
commit
4600a8d197
3 changed files with 864 additions and 803 deletions
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@ -1,3 +1,24 @@
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2010-09-01 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* config/arm/neon-schedgen.ml (core): New type.
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(allCores): List of supported cores.
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(availability_table): Add supported cores.
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(collate_bypasses): Accept core as a parameter.
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(worst_case_latencies_and_bypasses): Accept core as a
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parameter.
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(emit_insn_reservations): Accept core as a parameter.
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Use tuneStr and coreStr to get tune attribute and prefix
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for functional units.
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(emit_bypasses): Accept core name and use it.
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(calculate_per_core_availability_table): New.
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(filter_core): New.
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(calculate_core_availability_table): New.
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(main): Use calculate_core_availablity_table.
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* config/arm/cortex-a8-neon.md: Update copyright year.
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Regenerated from ml file and merged in.
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(neon_mrrc, neon_mrc): Rename to cortex_a8_neon_mrrc and
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cortex_a8_neon_mrc.
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2010-09-01 Ian Bolton <ian.bolton@arm.com>
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* Makefile.in (tree-switch-conversion.o): Update dependencies.
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File diff suppressed because it is too large
Load diff
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@ -1,7 +1,6 @@
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(* Emission of the core of the Cortex-A8 NEON scheduling description.
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Copyright (C) 2007, 2010 Free Software Foundation, Inc.
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Contributed by CodeSourcery.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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@ -21,7 +20,14 @@
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(* This scheduling description generator works as follows.
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- Each group of instructions has source and destination requirements
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specified. The source requirements may be specified using
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specified and a list of cores supported. This is then filtered
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and per core scheduler descriptions are generated out.
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The reservations generated are prefixed by the name of the
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core and the check is performed on the basis of what the tuning
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string is. Running this will generate Neon scheduler descriptions
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for all cores supported.
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The source requirements may be specified using
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Source (the stage at which all source operands not otherwise
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described are read), Source_m (the stage at which Rm operands are
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read), Source_n (likewise for Rn) and Source_d (likewise for Rd).
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@ -83,6 +89,17 @@ type reservation =
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| Ls of int
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| Fmul_then_fadd | Fmul_then_fadd_2
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type core = CortexA8 | CortexA9
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let allCores = [CortexA8]
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let coreStr = function
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CortexA8 -> "cortex_a8"
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| CortexA9 -> "cortex_a9"
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let tuneStr = function
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CortexA8 -> "cortexa8"
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| CortexA9 -> "cortexa9"
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(* This table must be kept as short as possible by conflating
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entries with the same availability behavior.
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@ -90,129 +107,136 @@ type reservation =
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Second components: availability requirements, in the order in which
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they should appear in the comments in the .md file.
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Third components: reservation info
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Fourth components: List of supported cores.
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*)
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let availability_table = [
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(* NEON integer ALU instructions. *)
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(* vbit vbif vbsl vorr vbic vnot vcls vclz vcnt vadd vand vorr
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veor vbic vorn ddd qqq *)
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"neon_int_1", [Source n2; Dest n3], ALU;
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"neon_int_1", [Source n2; Dest n3], ALU, allCores;
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(* vadd vsub qqd vsub ddd qqq *)
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"neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU;
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"neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU, allCores;
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(* vsum vneg dd qq vadd vsub qdd *)
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"neon_int_3", [Source n1; Dest n3], ALU;
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"neon_int_3", [Source n1; Dest n3], ALU, allCores;
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(* vabs vceqz vcgez vcbtz vclez vcltz vadh vradh vsbh vrsbh dqq *)
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(* vhadd vrhadd vqadd vtst ddd qqq *)
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"neon_int_4", [Source n2; Dest n4], ALU;
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"neon_int_4", [Source n2; Dest n4], ALU, allCores;
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(* vabd qdd vhsub vqsub vabd vceq vcge vcgt vmax vmin vfmx vfmn ddd ddd *)
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"neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU;
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"neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU, allCores;
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(* vqneg vqabs dd qq *)
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"neon_vqneg_vqabs", [Source n1; Dest n4], ALU;
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"neon_vqneg_vqabs", [Source n1; Dest n4], ALU, allCores;
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(* vmov vmvn *)
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"neon_vmov", [Dest n3], ALU;
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"neon_vmov", [Dest n3], ALU, allCores;
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(* vaba *)
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"neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU;
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"neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU, allCores;
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"neon_vaba_qqq",
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[Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ALU_2cycle;
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[Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)],
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ALU_2cycle, allCores;
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(* vsma *)
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"neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU;
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"neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU, allCores;
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(* NEON integer multiply instructions. *)
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(* vmul, vqdmlh, vqrdmlh *)
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(* vmul, vqdmul, qdd 16/8 long 32/16 long *)
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"neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], Mul;
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"neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], Mul_2cycle;
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"neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6],
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Mul, allCores;
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"neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)],
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Mul_2cycle, allCores;
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(* vmul, vqdmul again *)
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"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar",
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[Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle;
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[Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle, allCores;
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(* vmla, vmls *)
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"neon_mla_ddd_8_16_qdd_16_8_long_32_16_long",
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[Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul;
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[Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul, allCores;
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"neon_mla_qqq_8_16",
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[Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle;
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[Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)],
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Mul_2cycle, allCores;
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"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long",
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[Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle;
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[Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)],
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Mul_2cycle, allCores;
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"neon_mla_qqq_32_qqd_32_scalar",
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[Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], Mul_4cycle;
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[Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)],
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Mul_4cycle, allCores;
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(* vmul, vqdmulh, vqrdmulh *)
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(* vmul, vqdmul *)
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"neon_mul_ddd_16_scalar_32_16_long_scalar",
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[Source_n n2; Source_m n1; Dest n6], Mul;
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[Source_n n2; Source_m n1; Dest n6], Mul, allCores;
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"neon_mul_qqd_32_scalar",
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[Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle;
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[Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle, allCores;
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(* vmla, vmls *)
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(* vmla, vmla, vqdmla, vqdmls *)
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"neon_mla_ddd_16_scalar_qdd_32_16_long_scalar",
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[Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul;
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[Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul, allCores;
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(* NEON integer shift instructions. *)
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(* vshr/vshl immediate, vshr_narrow, vshl_vmvh, vsli_vsri_ddd *)
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"neon_shift_1", [Source n1; Dest n3], Shift;
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(* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow;
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"neon_shift_1", [Source n1; Dest n3], Shift, allCores;
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(* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow, allCores;
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vqshl_vrshl_vqrshl_ddd *)
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"neon_shift_2", [Source n1; Dest n4], Shift;
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"neon_shift_2", [Source n1; Dest n4], Shift, allCores;
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(* vsli, vsri and vshl for qqq *)
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"neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle;
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"neon_vshl_ddd", [Source n1; Dest n1], Shift;
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"neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle, allCores;
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"neon_vshl_ddd", [Source n1; Dest n1], Shift, allCores;
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"neon_vqshl_vrshl_vqrshl_qqq", [Source n1; Dest_n_after (1, n4)],
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Shift_2cycle;
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"neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift;
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Shift_2cycle, allCores;
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"neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift, allCores;
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(* NEON floating-point instructions. *)
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(* vadd, vsub, vabd, vmul, vceq, vcge, vcgt, vcage, vcagt, vmax, vmin *)
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(* vabs, vneg, vceqz, vcgez, vcgtz, vclez, vcltz, vrecpe, vrsqrte, vcvt *)
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"neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd;
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"neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd, allCores;
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"neon_fp_vadd_qqq_vabs_qq", [Source n2; Dest_n_after (1, n5)],
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Fadd_2cycle;
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Fadd_2cycle, allCores;
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(* vsum, fvmx, vfmn *)
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"neon_fp_vsum", [Source n1; Dest n5], Fadd;
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"neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul;
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"neon_fp_vsum", [Source n1; Dest n5], Fadd, allCores;
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"neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul, allCores;
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"neon_fp_vmul_qqd", [Source_n n2; Source_m n1; Dest_n_after (1, n5)],
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Fmul_2cycle;
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Fmul_2cycle, allCores;
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(* vmla, vmls *)
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"neon_fp_vmla_ddd",
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[Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd;
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[Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd, allCores;
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"neon_fp_vmla_qqq",
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[Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n9)],
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Fmul_then_fadd_2;
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Fmul_then_fadd_2, allCores;
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"neon_fp_vmla_ddd_scalar",
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[Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd;
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[Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd, allCores;
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"neon_fp_vmla_qqq_scalar",
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[Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n9)],
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Fmul_then_fadd_2;
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"neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd;
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Fmul_then_fadd_2, allCores;
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"neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd, allCores;
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"neon_fp_vrecps_vrsqrts_qqq", [Source n2; Dest_n_after (1, n9)],
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Fmul_then_fadd_2;
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Fmul_then_fadd_2, allCores;
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(* NEON byte permute instructions. *)
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(* vmov; vtrn and vswp for dd; vzip for dd; vuzp for dd; vrev; vext for dd *)
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"neon_bp_simple", [Source n1; Dest n2], Permute 1;
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(* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1};
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"neon_bp_simple", [Source n1; Dest n2], Permute 1, allCores;
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(* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1}, allCores;
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similarly for vtbx *)
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"neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2;
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"neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2, allCores;
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(* all the rest *)
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"neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3;
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"neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3, allCores;
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(* NEON load/store instructions. *)
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"neon_ldr", [Dest n1], Ls 1;
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"neon_str", [Source n1], Ls 1;
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"neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2;
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"neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3;
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"neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2;
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"neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3;
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"neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4;
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"neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2;
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"neon_vst1_3_4_regs", [Source n1], Ls 3;
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"neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4;
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"neon_vst3_vst4", [Source n1], Ls 4;
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"neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3;
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"neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5;
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"neon_vst1_vst2_lane", [Source n1], Ls 2;
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"neon_vst3_vst4_lane", [Source n1], Ls 3;
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"neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3;
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"neon_ldr", [Dest n1], Ls 1, allCores;
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"neon_str", [Source n1], Ls 1, allCores;
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"neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2, allCores;
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"neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3, allCores;
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"neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2, allCores;
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"neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3, allCores;
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"neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4, allCores;
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"neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2, allCores;
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"neon_vst1_3_4_regs", [Source n1], Ls 3, allCores;
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"neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4, allCores;
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"neon_vst3_vst4", [Source n1], Ls 4, allCores;
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"neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3, allCores;
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"neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5, allCores;
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"neon_vst1_vst2_lane", [Source n1], Ls 2, allCores;
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"neon_vst3_vst4_lane", [Source n1], Ls 3, allCores;
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"neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3, allCores;
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(* NEON register transfer instructions. *)
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"neon_mcr", [Dest n2], Permute 1;
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"neon_mcr_2_mcrr", [Dest n2], Permute 2;
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"neon_mcr", [Dest n2], Permute 1, allCores;
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"neon_mcr_2_mcrr", [Dest n2], Permute 2, allCores;
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(* MRC instructions are in the .tpl file. *)
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]
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@ -221,7 +245,7 @@ let availability_table = [
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required. (It is also possible that an entry in the table has no
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source requirements.) *)
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let calculate_sources =
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List.map (fun (name, avail, res) ->
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List.map (fun (name, avail, res, cores) ->
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let earliest_stage =
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List.fold_left
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(fun cur -> fun info ->
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@ -331,7 +355,7 @@ let pick_latency largest worst guards =
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of one bypass from this producer to any particular consumer listed
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in LATENCIES.) Use a hash table to collate bypasses with the
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same latency and guard. *)
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let collate_bypasses (producer_name, _, _, _) largest latencies =
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let collate_bypasses (producer_name, _, _, _) largest latencies core =
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let ht = Hashtbl.create 42 in
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let keys = ref [] in
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List.iter (
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@ -350,7 +374,7 @@ let collate_bypasses (producer_name, _, _, _) largest latencies =
|
|||
(if (try ignore (Hashtbl.find ht (guard, latency)); false
|
||||
with Not_found -> true) then
|
||||
keys := (guard, latency) :: !keys);
|
||||
Hashtbl.add ht (guard, latency) consumer
|
||||
Hashtbl.add ht (guard, latency) ((coreStr core) ^ "_" ^ consumer)
|
||||
end
|
||||
) latencies;
|
||||
(* The hash table now has bypasses collated so that ones with the
|
||||
|
|
@ -372,7 +396,7 @@ let collate_bypasses (producer_name, _, _, _) largest latencies =
|
|||
the output in such a way that all bypasses with the same producer
|
||||
and latency are together, and so that bypasses with the worst-case
|
||||
latency are ignored. *)
|
||||
let worst_case_latencies_and_bypasses =
|
||||
let worst_case_latencies_and_bypasses core =
|
||||
let rec f (worst_acc, bypasses_acc) prev xs =
|
||||
match xs with
|
||||
[] -> (worst_acc, bypasses_acc)
|
||||
|
|
@ -400,7 +424,7 @@ let worst_case_latencies_and_bypasses =
|
|||
(* Having got the largest latency, collect all bypasses for
|
||||
this producer and filter out those with that larger
|
||||
latency. Record the others for later emission. *)
|
||||
let bypasses = collate_bypasses producer largest latencies in
|
||||
let bypasses = collate_bypasses producer largest latencies core in
|
||||
(* Go on to process remaining producers, having noted
|
||||
the result for this one. *)
|
||||
f ((producer_name, producer_avail, largest,
|
||||
|
|
@ -444,14 +468,18 @@ let write_comment producer avail =
|
|||
in
|
||||
f avail 0
|
||||
|
||||
|
||||
(* Emit a define_insn_reservation for each producer. The latency
|
||||
written in will be its worst-case latency. *)
|
||||
let emit_insn_reservations =
|
||||
List.iter (
|
||||
let emit_insn_reservations core =
|
||||
let corestring = coreStr core in
|
||||
let tunestring = tuneStr core
|
||||
in List.iter (
|
||||
fun (producer, avail, latency, reservation) ->
|
||||
write_comment producer avail;
|
||||
Printf.printf "(define_insn_reservation \"%s\" %d\n" producer latency;
|
||||
Printf.printf " (and (eq_attr \"tune\" \"cortexa8\")\n";
|
||||
Printf.printf "(define_insn_reservation \"%s_%s\" %d\n"
|
||||
corestring producer latency;
|
||||
Printf.printf " (and (eq_attr \"tune\" \"%s\")\n" tunestring;
|
||||
Printf.printf " (eq_attr \"neon_type\" \"%s\"))\n" producer;
|
||||
let str =
|
||||
match reservation with
|
||||
|
|
@ -467,7 +495,7 @@ let emit_insn_reservations =
|
|||
| Fmul_then_fadd -> "fmul_then_fadd"
|
||||
| Fmul_then_fadd_2 -> "fmul_then_fadd_2"
|
||||
in
|
||||
Printf.printf " \"cortex_a8_neon_%s\")\n\n" str
|
||||
Printf.printf " \"%s_neon_%s\")\n\n" corestring str
|
||||
)
|
||||
|
||||
(* Given a guard description, return the name of the C function to
|
||||
|
|
@ -480,10 +508,12 @@ let guard_fn g =
|
|||
| Guard_none -> assert false
|
||||
|
||||
(* Emit a define_bypass for each bypass. *)
|
||||
let emit_bypasses =
|
||||
let emit_bypasses core =
|
||||
List.iter (
|
||||
fun (producer, consumers, latency, guard) ->
|
||||
Printf.printf "(define_bypass %d \"%s\"\n" latency producer;
|
||||
Printf.printf "(define_bypass %d \"%s_%s\"\n"
|
||||
latency (coreStr core) producer;
|
||||
|
||||
if guard = Guard_none then
|
||||
Printf.printf " \"%s\")\n\n" consumers
|
||||
else
|
||||
|
|
@ -493,11 +523,21 @@ let emit_bypasses =
|
|||
end
|
||||
)
|
||||
|
||||
|
||||
let calculate_per_core_availability_table core availability_table =
|
||||
let table = calculate_sources availability_table in
|
||||
let worst_cases, bypasses = worst_case_latencies_and_bypasses core table in
|
||||
emit_insn_reservations core (List.rev worst_cases);
|
||||
Printf.printf ";; Exceptions to the default latencies.\n\n";
|
||||
emit_bypasses core bypasses
|
||||
|
||||
let calculate_core_availability_table core availability_table =
|
||||
let filter_core = List.filter (fun (_, _, _, cores)
|
||||
-> List.exists ((=) core) cores)
|
||||
in calculate_per_core_availability_table core (filter_core availability_table)
|
||||
|
||||
|
||||
(* Program entry point. *)
|
||||
let main =
|
||||
let table = calculate_sources availability_table in
|
||||
let worst_cases, bypasses = worst_case_latencies_and_bypasses table in
|
||||
emit_insn_reservations (List.rev worst_cases);
|
||||
Printf.printf ";; Exceptions to the default latencies.\n\n";
|
||||
emit_bypasses bypasses
|
||||
|
||||
List.map (fun core -> calculate_core_availability_table
|
||||
core availability_table) allCores
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue