Daily bump.
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5 changed files with 95 additions and 1 deletions
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2023-11-05 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.h (enum reg_class): Add LEGACY_INDEX_REGS.
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Rename LEGACY_REGS to LEGACY_GENERAL_REGS.
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(REG_CLASS_NAMES): Ditto.
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(REG_CLASS_CONTENTS): Ditto.
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* config/i386/constraints.md ("R"): Update for rename.
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2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
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* mode-switching.cc: Remove unused forward references.
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(seginfo): Remove bbnum.
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(new_seginfo): Remove associated argument.
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(optimize_mode_switching): Update calls accordingly.
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2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
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* read-rtl.cc (read_rtx_operand): Avoid spinning endlessly for
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invalid [...] operands.
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2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
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PR target/112105
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* config/aarch64/aarch64.cc (aarch64_modes_compatible_p): New
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function, with the core logic extracted from...
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(aarch64_can_change_mode_class): ...here. Extend the previous rules
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to allow changes between partial SVE modes and other modes if
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the other mode is no bigger than an element, and if no other rule
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prevents it. Use the aarch64_modes_tieable_p handling of
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partial Advanced SIMD structure modes.
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(aarch64_modes_tieable_p): Use aarch64_modes_compatible_p.
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Allow all vector mode ties that it allows.
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2023-11-05 Pan Li <pan2.li@intel.com>
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* config/riscv/autovec.md: Remove the size check of lrint.
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* config/riscv/riscv-v.cc (emit_vec_narrow_cvt_x_f): New help
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emit func impl.
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(emit_vec_widden_cvt_x_f): New help emit func impl.
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(emit_vec_rounding_to_integer): New func impl to emit the
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rounding from FP to integer.
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(expand_vec_lrint): Leverage emit_vec_rounding_to_integer.
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* config/riscv/vector.md: Take V_VLSF for vfncvt.
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2023-11-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
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* config/riscv/vector.md: Fix bug.
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2023-11-04 Sergei Trofimovich <siarheit@google.com>
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PR bootstrap/112379
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@ -1 +1 @@
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20231105
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20231106
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2023-11-05 Jakub Jelinek <jakub@redhat.com>
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* c-lex.cc (c_common_has_attribute): Return 1 for omp::directive
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and omp::sequence with -fopenmp or -fopenmp-simd also for C, not
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just for C++. Return 1 for omp::decl with -fopenmp or -fopenmp-simd
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for both C and C++.
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2023-11-04 David Malcolm <dmalcolm@redhat.com>
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* c-pragma.cc:: (handle_pragma_push_options): Fix missing "GCC" in
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2023-11-05 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
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* gcc.target/i386/pr111753.c: Require dfp.
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2023-11-05 Jakub Jelinek <jakub@redhat.com>
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* c-c++-common/gomp/attrs-1.c: Adjust for omp::directive and
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omp::sequence being supported also in C and add tests for omp::decl.
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* c-c++-common/gomp/attrs-2.c: Likewise.
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* c-c++-common/gomp/attrs-3.c: Add tests for omp::decl.
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2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
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PR target/112105
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* gcc.target/aarch64/pr112105.c: New test.
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* gcc.target/aarch64/sve/pcs/struct_3_128.c: Expect a 32-bit spill
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rather than a 16-bit spill.
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2023-11-05 Pan Li <pan2.li@intel.com>
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* gcc.target/riscv/rvv/autovec/unop/math-irint-run-0.c:
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* gcc.target/riscv/rvv/autovec/unop/math-irint-1.c: New test.
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* gcc.target/riscv/rvv/autovec/unop/math-irintf-run-0.c: New test.
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* gcc.target/riscv/rvv/autovec/unop/math-llrintf-0.c: New test.
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* gcc.target/riscv/rvv/autovec/unop/math-llrintf-run-0.c: New test.
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* gcc.target/riscv/rvv/autovec/unop/math-lrint-rv32-0.c: New test.
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* gcc.target/riscv/rvv/autovec/unop/math-lrint-rv32-run-0.c: New test.
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* gcc.target/riscv/rvv/autovec/unop/math-lrintf-rv64-0.c: New test.
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* gcc.target/riscv/rvv/autovec/unop/math-lrintf-rv64-run-0.c: New test.
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* gcc.target/riscv/rvv/autovec/vls/math-irint-1.c: New test.
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* gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c: New test.
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* gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c: New test.
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* gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c: New test.
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2023-11-04 Jakub Jelinek <jakub@redhat.com>
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* gcc.dg/gomp/attrs-19.c: New test.
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2023-11-05 Jakub Jelinek <jakub@redhat.com>
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* libgomp.texi (Enabling OpenMP): Adjust wording for attribute syntax
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supported also in C.
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2023-10-31 Thomas Schwinge <thomas@codesourcery.com>
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* testsuite/libgomp.oacc-c-c++-common/deep-copy-8.c: Add OpenACC
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