i386.c (print_reg): Use ANY_FP_REG instead of FP_REG
* i386.c (print_reg): Use ANY_FP_REG instead of FP_REG * i386.h (MASK_128BIT_LONG_DOUBLE): Renumber (MASK_SSE2): New. (MASK_MIX_SSE_I387): New. (TARGET_SSE): SSE2 imply SSE. (TARGET_SSE2, TARGET_MIX_SSE_I387): New. (TARGET_SWITCHES): Add "sse2", "mix-sse-i387". (enum reg_class): Add new classes. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Likewise. (ANY_FP_REG_P, ANY_FP_REGNO_P, SSE_REG_P, SSE_FLOAT_MODE): New macros. (REG_CLASS_FROM_LETTER): 'x' and 'y' is SSE_REGS only when SSE is supported. Add 'Y' to be SSE_REGS when SSE2 is supported. (CLASS_MAX_NREGS): Use new macros. (REGISTER_MOVE_COST): Rewrite using SECONDARY_MEMORY_MAYBE_NEEDED. * i386.md (pushsf, movsf): Support SSE. (pushdf_nointeger, pushdf_integer, pushdf): Support SSE, update splitters to use ANY_FP_REGNO_P. (movdf_nointeger, movdf_integer): Likewise. From-SVN: r39628
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
c26a370f75
commit
446988df3b
4 changed files with 146 additions and 71 deletions
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@ -1,3 +1,25 @@
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Tue Feb 13 13:31:33 CET 2001 Jan Hubicka <jh@suse.cz>
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* i386.c (print_reg): Use ANY_FP_REG instead of FP_REG
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* i386.h (MASK_128BIT_LONG_DOUBLE): Renumber
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(MASK_SSE2): New.
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(MASK_MIX_SSE_I387): New.
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(TARGET_SSE): SSE2 imply SSE.
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(TARGET_SSE2, TARGET_MIX_SSE_I387): New.
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(TARGET_SWITCHES): Add "sse2", "mix-sse-i387".
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(enum reg_class): Add new classes.
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(REG_CLASS_NAMES): Likewise.
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(REG_CLASS_CONTENTS): Likewise.
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(ANY_FP_REG_P, ANY_FP_REGNO_P, SSE_REG_P, SSE_FLOAT_MODE): New macros.
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(REG_CLASS_FROM_LETTER): 'x' and 'y' is SSE_REGS only when SSE is
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supported. Add 'Y' to be SSE_REGS when SSE2 is supported.
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(CLASS_MAX_NREGS): Use new macros.
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(REGISTER_MOVE_COST): Rewrite using SECONDARY_MEMORY_MAYBE_NEEDED.
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* i386.md (pushsf, movsf): Support SSE.
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(pushdf_nointeger, pushdf_integer, pushdf): Support SSE, update
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splitters to use ANY_FP_REGNO_P.
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(movdf_nointeger, movdf_integer): Likewise.
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2001-02-13 Alexandre Oliva <aoliva@redhat.com>
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* combine.c (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD): New macro.
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@ -3285,7 +3285,7 @@ print_reg (x, code, file)
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case 4:
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case 8:
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case 12:
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if (! FP_REG_P (x))
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if (! ANY_FP_REG_P (x))
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putc ('e', file);
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/* FALLTHRU */
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case 16:
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@ -104,7 +104,9 @@ extern int target_flags;
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#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00008000/* Accumulate outgoing args */
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#define MASK_MMX 0x00010000 /* Support MMX regs/builtins */
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#define MASK_SSE 0x00020000 /* Support SSE regs/builtins */
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#define MASK_128BIT_LONG_DOUBLE 0x00040000 /* long double size is 128bit */
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#define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
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#define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
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#define MASK_MIX_SSE_I387 0x00100000 /* Mix SSE and i387 instructions */
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/* Temporary codegen switches */
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#define MASK_INTEL_SYNTAX 0x00000200
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@ -226,7 +228,9 @@ extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
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#define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
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#define TARGET_SSE ((target_flags & MASK_SSE) != 0)
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#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
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#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
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#define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
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#define TARGET_MMX ((target_flags & MASK_MMX) != 0)
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#define TARGET_SWITCHES \
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@ -298,9 +302,17 @@ extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
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{ "no-mmx", -MASK_MMX, \
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N_("Do not support MMX builtins") }, \
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{ "sse", MASK_SSE, \
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N_("Support MMX and SSE builtins") }, \
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N_("Support MMX and SSE builtins and code generation") }, \
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{ "no-sse", -MASK_SSE, \
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N_("Do not support MMX and SSE builtins") }, \
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N_("Do not support MMX and SSE builtins and code generation") }, \
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{ "sse2", MASK_SSE2, \
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N_("Support MMX, SSE and SSE2 builtins and code generation") }, \
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{ "no-sse2", -MASK_SSE2, \
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N_("Do not support MMX, SSE and SSE2 builtins and code generation") }, \
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{ "mix-sse-i387", MASK_MIX_SSE_I387, \
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N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
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{ "nomix-sse-i387", -MASK_MIX_SSE_I387, \
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N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
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{ "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
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N_("sizeof(long double) is 16.") }, \
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{ "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
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@ -765,7 +777,8 @@ extern int ix86_arch;
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: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
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#define VALID_SSE_REG_MODE(MODE) \
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((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode)
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((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
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|| (MODE) == SFmode || (TARGET_SSE2 && (MODE) == DFmode))
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#define VALID_MMX_REG_MODE(MODE) \
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((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
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@ -939,7 +952,12 @@ enum reg_class
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FLOAT_REGS,
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SSE_REGS,
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MMX_REGS,
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FLOAT_INT_REGS, /* FLOAT_REGS and GENERAL_REGS. */
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FP_TOP_SSE_REGS,
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FP_SECOND_SSE_REGS,
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FLOAT_SSE_REGS,
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FLOAT_INT_REGS,
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INT_SSE_REGS,
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FLOAT_INT_SSE_REGS,
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ALL_REGS, LIM_REG_CLASSES
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};
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@ -968,7 +986,12 @@ enum reg_class
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"FLOAT_REGS", \
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"SSE_REGS", \
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"MMX_REGS", \
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"FP_TOP_SSE_REGS", \
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"FP_SECOND_SSE_REGS", \
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"FLOAT_SSE_REGS", \
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"FLOAT_INT_REGS", \
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"INT_SSE_REGS", \
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"FLOAT_INT_SSE_REGS", \
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"ALL_REGS" }
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/* Define which registers fit in which classes.
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@ -989,7 +1012,12 @@ enum reg_class
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{ 0xff00, 0x0 }, /* FLOAT_REGS */ \
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{ 0x1fe00000, 0x0 }, /* SSE_REGS */ \
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{ 0xe0000000, 0x1f }, /* MMX_REGS */ \
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{ 0x1fe00100, 0x0 }, /* FP_TOP_SSE_REG */ \
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{ 0x1fe00200, 0x0 }, /* FP_SECOND_SSE_REG */ \
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{ 0x1fe0ff00, 0x0 }, /* FLOAT_SSE_REGS */ \
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{ 0x1ffff, 0x0 }, /* FLOAT_INT_REGS */ \
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{ 0x1fe100ff, 0x0 }, /* INT_SSE_REGS */ \
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{ 0x1fe1ffff, 0x0 }, /* FLOAT_INT_SSE_REGS */ \
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{ 0xffffffff, 0x1f } \
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}
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@ -1013,8 +1041,14 @@ enum reg_class
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#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
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#define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
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#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
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#define ANY_FP_REGNO_P(n) (FP_REGNO_P (n) || SSE_REGNO_P (n))
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#define SSE_REGNO_P(n) ((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG)
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#define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
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#define SSE_FLOAT_MODE_P(m) \
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((TARGET_SSE && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
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#define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
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#define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
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@ -1058,8 +1092,9 @@ enum reg_class
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(C) == 'b' ? BREG : \
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(C) == 'c' ? CREG : \
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(C) == 'd' ? DREG : \
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(C) == 'x' ? SSE_REGS : \
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(C) == 'y' ? MMX_REGS : \
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(C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
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(C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
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(C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
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(C) == 'A' ? AD_REGS : \
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(C) == 'D' ? DIREG : \
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(C) == 'S' ? SIREG : NO_REGS)
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@ -2100,8 +2100,8 @@
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"ix86_expand_move (SFmode, operands); DONE;")
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(define_insn "*pushsf"
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[(set (match_operand:SF 0 "push_operand" "=<,<")
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(match_operand:SF 1 "general_no_elim_operand" "f#r,rFm#f"))]
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[(set (match_operand:SF 0 "push_operand" "=<,<,<")
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(match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x"))]
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""
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"*
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{
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@ -2119,13 +2119,15 @@
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case 1:
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return \"push{l}\\t%1\";
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case 2:
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return \"#\";
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default:
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abort ();
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}
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}"
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[(set_attr "type" "multi,push")
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(set_attr "mode" "SF,SI")])
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[(set_attr "type" "multi,push,multi")
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(set_attr "mode" "SF,SI,SF")])
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(define_split
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[(set (match_operand:SF 0 "push_operand" "")
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@ -2143,13 +2145,13 @@
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(define_split
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[(set (match_operand:SF 0 "push_operand" "")
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(match_operand:SF 1 "register_operand" ""))]
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"FP_REGNO_P (REGNO (operands[1]))"
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"ANY_FP_REGNO_P (REGNO (operands[1]))"
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[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
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(set (mem:SF (reg:SI 7)) (match_dup 1))])
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(define_insn "*movsf_1"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,m")
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(match_operand:SF 1 "general_operand" "fm#r,f#r,G,rmF#f,Fr#f"))]
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,m")
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(match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,xm#rf,x#rf"))]
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"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
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&& (reload_in_progress || reload_completed
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|| GET_CODE (operands[1]) != CONST_DOUBLE
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@ -2186,13 +2188,16 @@
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case 3:
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case 4:
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return \"mov{l}\\t{%1, %0|%0, %1}\";
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case 5:
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case 6:
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return \"movss\\t{%1, %0|%0, %1}\";
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default:
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abort();
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}
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}"
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[(set_attr "type" "fmov,fmov,fmov,imov,imov")
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(set_attr "mode" "SF,SF,SF,SI,SI")])
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[(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse")
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(set_attr "mode" "SF,SF,SF,SI,SI,SF,SF")])
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(define_split
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[(set (match_operand:SF 0 "nonimmediate_operand" "")
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@ -2201,6 +2206,8 @@
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&& GET_CODE (operands[1]) == MEM
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&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
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&& CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
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&& !(SSE_REG_P (operands[0])
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|| (GET_CODE (operands[0]) == SUBREG && SSE_REG_P (operands[0])))
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&& (!(FP_REG_P (operands[0]) ||
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(GET_CODE (operands[0]) == SUBREG
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&& FP_REG_P (SUBREG_REG (operands[0]))))
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@ -2214,7 +2221,7 @@
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(match_operand:SF 1 "register_operand" "+f"))
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(set (match_dup 1)
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(match_dup 0))]
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""
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"reload_completed || !TARGET_SSE2"
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"*
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{
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if (STACK_TOP_P (operands[0]))
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@ -2237,8 +2244,8 @@
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;; pattern for optimize_size too.
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(define_insn "*pushdf_nointeger"
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[(set (match_operand:DF 0 "push_operand" "=<,<,<")
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(match_operand:DF 1 "general_no_elim_operand" "f,Fo#f,*r#f"))]
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[(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
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(match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y"))]
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"!TARGET_INTEGER_DFMODE_MOVES"
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"*
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{
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@ -2254,6 +2261,36 @@
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else
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return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
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case 1:
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case 2:
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case 3:
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return \"#\";
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default:
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abort ();
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}
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}"
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[(set_attr "type" "multi")
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(set_attr "mode" "DF,SI,SI,DF")])
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(define_insn "*pushdf_integer"
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[(set (match_operand:DF 0 "push_operand" "=<,<,<")
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(match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
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"TARGET_INTEGER_DFMODE_MOVES"
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"*
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{
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switch (which_alternative)
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{
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case 0:
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/* %%% We loose REG_DEAD notes for controling pops if we split late. */
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operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
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operands[2] = stack_pointer_rtx;
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operands[3] = GEN_INT (8);
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if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
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return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
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else
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return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
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case 1:
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case 2:
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return \"#\";
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@ -2263,41 +2300,13 @@
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}
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}"
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[(set_attr "type" "multi")
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(set_attr "mode" "DF,SI,SI")])
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(define_insn "*pushdf_integer"
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[(set (match_operand:DF 0 "push_operand" "=<,<")
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(match_operand:DF 1 "general_no_elim_operand" "f#r,rFo#f"))]
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"TARGET_INTEGER_DFMODE_MOVES"
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"*
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{
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switch (which_alternative)
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{
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case 0:
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/* %%% We loose REG_DEAD notes for controling pops if we split late. */
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operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
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operands[2] = stack_pointer_rtx;
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operands[3] = GEN_INT (8);
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if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
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return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
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else
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return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
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case 1:
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return \"#\";
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default:
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abort ();
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}
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}"
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[(set_attr "type" "multi")
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(set_attr "mode" "DF,SI")])
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(set_attr "mode" "DF,SI,DF")])
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;; %%% Kill this when call knows how to work this out.
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(define_split
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[(set (match_operand:DF 0 "push_operand" "")
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(match_operand:DF 1 "register_operand" ""))]
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"reload_completed && FP_REGNO_P (REGNO (operands[1]))"
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"reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
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[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
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(set (mem:DF (reg:SI 7)) (match_dup 1))]
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"")
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@ -2314,8 +2323,8 @@
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;; when optimizing for size.
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(define_insn "*movdf_nointeger"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,f,*r,o")
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(match_operand:DF 1 "general_operand" "fm,f,G,*roF,F*r"))]
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,m")
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(match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,Ym#f,Y#f"))]
|
||||
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
|
||||
&& (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
|
||||
&& (reload_in_progress || reload_completed
|
||||
|
|
@ -2353,17 +2362,20 @@
|
|||
case 3:
|
||||
case 4:
|
||||
return \"#\";
|
||||
case 5:
|
||||
case 6:
|
||||
return \"movsd\\t{%1, %0|%0, %1}\";
|
||||
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
|
||||
(set_attr "mode" "DF,DF,DF,SI,SI")])
|
||||
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse")
|
||||
(set_attr "mode" "DF,DF,DF,SI,SI,DF,DF")])
|
||||
|
||||
(define_insn "*movdf_integer"
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
|
||||
(match_operand:DF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,m")
|
||||
(match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,Ym#rf,Y#rf"))]
|
||||
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
|
||||
&& !optimize_size && TARGET_INTEGER_DFMODE_MOVES
|
||||
&& (reload_in_progress || reload_completed
|
||||
|
|
@ -2402,24 +2414,28 @@
|
|||
case 4:
|
||||
return \"#\";
|
||||
|
||||
case 5:
|
||||
case 6:
|
||||
return \"movsd\\t{%1, %0|%0, %1}\";
|
||||
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
|
||||
(set_attr "mode" "DF,DF,DF,SI,SI")])
|
||||
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse")
|
||||
(set_attr "mode" "DF,DF,DF,SI,SI,DF,DF")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "")
|
||||
(match_operand:DF 1 "general_operand" ""))]
|
||||
"reload_completed
|
||||
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
|
||||
&& ! (FP_REG_P (operands[0]) ||
|
||||
&& ! (ANY_FP_REG_P (operands[0]) ||
|
||||
(GET_CODE (operands[0]) == SUBREG
|
||||
&& FP_REG_P (SUBREG_REG (operands[0]))))
|
||||
&& ! (FP_REG_P (operands[1]) ||
|
||||
&& ANY_FP_REG_P (SUBREG_REG (operands[0]))))
|
||||
&& ! (ANY_FP_REG_P (operands[1]) ||
|
||||
(GET_CODE (operands[1]) == SUBREG
|
||||
&& FP_REG_P (SUBREG_REG (operands[1]))))"
|
||||
&& ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
|
||||
[(set (match_dup 2) (match_dup 5))
|
||||
(set (match_dup 3) (match_dup 6))]
|
||||
"if (ix86_split_long_move (operands)) DONE;")
|
||||
|
|
@ -2431,6 +2447,8 @@
|
|||
&& GET_CODE (operands[1]) == MEM
|
||||
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
|
||||
&& CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
|
||||
&& !(SSE_REG_P (operands[0])
|
||||
|| (GET_CODE (operands[0]) == SUBREG && SSE_REG_P (operands[0])))
|
||||
&& standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0)))"
|
||||
[(set (match_dup 0)
|
||||
(match_dup 1))]
|
||||
|
|
@ -2441,7 +2459,7 @@
|
|||
(match_operand:DF 1 "register_operand" "+f"))
|
||||
(set (match_dup 1)
|
||||
(match_dup 0))]
|
||||
""
|
||||
"reload_completed || !TARGET_SSE2"
|
||||
"*
|
||||
{
|
||||
if (STACK_TOP_P (operands[0]))
|
||||
|
|
@ -2592,21 +2610,21 @@
|
|||
&& (GET_MODE (operands[0]) == XFmode
|
||||
|| GET_MODE (operands[0]) == TFmode
|
||||
|| GET_MODE (operands[0]) == DFmode)
|
||||
&& (!REG_P (operands[1]) || !FP_REGNO_P (REGNO (operands[1])))"
|
||||
&& (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
|
||||
[(const_int 0)]
|
||||
"if (!ix86_split_long_move (operands)) abort (); DONE;")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:XF 0 "push_operand" "")
|
||||
(match_operand:XF 1 "register_operand" ""))]
|
||||
"FP_REGNO_P (REGNO (operands[1]))"
|
||||
"ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
|
||||
(set (mem:XF (reg:SI 7)) (match_dup 1))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:TF 0 "push_operand" "")
|
||||
(match_operand:TF 1 "register_operand" ""))]
|
||||
"FP_REGNO_P (REGNO (operands[1]))"
|
||||
"ANY_FP_REGNO_P (REGNO (operands[1]))"
|
||||
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
|
||||
(set (mem:TF (reg:SI 7)) (match_dup 1))])
|
||||
|
||||
|
|
@ -2805,12 +2823,12 @@
|
|||
"reload_completed
|
||||
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
|
||||
&& (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
|
||||
&& ! (FP_REG_P (operands[0]) ||
|
||||
&& ! (ANY_FP_REG_P (operands[0]) ||
|
||||
(GET_CODE (operands[0]) == SUBREG
|
||||
&& FP_REG_P (SUBREG_REG (operands[0]))))
|
||||
&& ! (FP_REG_P (operands[1]) ||
|
||||
&& ANY_FP_REG_P (SUBREG_REG (operands[0]))))
|
||||
&& ! (ANY_FP_REG_P (operands[1]) ||
|
||||
(GET_CODE (operands[1]) == SUBREG
|
||||
&& FP_REG_P (SUBREG_REG (operands[1]))))"
|
||||
&& ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
|
||||
[(set (match_dup 2) (match_dup 5))
|
||||
(set (match_dup 3) (match_dup 6))
|
||||
(set (match_dup 4) (match_dup 7))]
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue