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RISC-V: Change truncate to float_truncate in narrowing patterns.

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This fixes a bug in the autovect FP narrowing patterns which resulted in
a combine ICE.  It would try to e.g. simplify a unary operation by
simplify_const_unary_operation which obviously expects a float_truncate
and not a truncate for a floating-point mode.

gcc/ChangeLog:

	* config/riscv/autovec.md: Use float_truncate.
This commit is contained in:
Robin Dapp 2023-07-05 14:42:21 +02:00
parent 34c614b7e9
commit 429905d809
1 changed files with 2 additions and 2 deletions
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4
gcc/config/riscv/autovec.md
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@ -473,7 +473,7 @@
;; -------------------------------------------------------------------------
(define_insn_and_split "trunc<mode><v_double_trunc>2"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vr")
(truncate:<V_DOUBLE_TRUNC>
(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF_ZVFHMIN 1 "register_operand" " vr")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
@ -493,7 +493,7 @@
;; -------------------------------------------------------------------------
(define_expand "trunc<mode><v_quad_trunc>2"
[(set (match_operand:<V_QUAD_TRUNC> 0 "register_operand")
(truncate:<V_QUAD_TRUNC>
(float_truncate:<V_QUAD_TRUNC>
(match_operand:VQEXTF 1 "register_operand")))]
"TARGET_VECTOR && (TARGET_ZVFHMIN || TARGET_ZVFH)"
{