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RISC-V: Fix vector SAT_ADD dump check due to middle-end change

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This patch would like fix the dump check times of vector SAT_ADD.  The
middle-end change makes the match times from 2 to 4 times.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Adjust
	the dump check times from 2 to 4.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li 2024-09-11 14:17:30 +08:00
parent e917a251d8
commit 427f824258
16 changed files with 16 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_6(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_6(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_6(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_6(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_7(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_7(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_7(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_7(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_8(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_8(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_8(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_8(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_2(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_2(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_2(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
View file

@ -15,4 +15,4 @@
*/
DEF_VEC_SAT_U_ADD_FMT_2(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */