Fix memory constraint on MVE v[ld/st][2/4] instructions [PR107714]
In the M-Class Arm-ARM: https://developer.arm.com/documentation/ddi0553/bu/?lang=en these MVE instructions only have '!' writeback variant and at: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107714 we found that the Um constraint would also allow through a register offset writeback, resulting in an assembler error. Here I have added a new constraint and predicate for these instructions, which (uniquely, AFAICT), only support a `!` writeback increment by the data size (inside the compiler this is a POST_INC). No regressions in arm-none-eabi with MVE and MVE.FP. gcc/ChangeLog: PR target/107714 * config/arm/arm-protos.h (mve_struct_mem_operand): New protoype. * config/arm/arm.cc (mve_struct_mem_operand): New function. * config/arm/constraints.md (Ug): New constraint. * config/arm/mve.md (mve_vst4q<mode>): Change constraint. (mve_vst2q<mode>): Likewise. (mve_vld4q<mode>): Likewise. (mve_vld2q<mode>): Likewise. * config/arm/predicates.md (mve_struct_operand): New predicate. gcc/testsuite/ChangeLog: PR target/107714 * gcc.target/arm/mve/intrinsics/vldst24q_reg_offset.c: New test.
This commit is contained in:
Stam Markianos-Wright
parent
cdc6bf44ee
commit
4269a6567e
6 changed files with 332 additions and 4 deletions
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@ -122,6 +122,7 @@ extern int arm_coproc_mem_operand_wb (rtx, int);
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extern int neon_vector_mem_operand (rtx, int, bool);
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extern int mve_vector_mem_operand (machine_mode, rtx, bool);
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extern int neon_struct_mem_operand (rtx);
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extern int mve_struct_mem_operand (rtx);
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extern rtx *neon_vcmla_lane_prepare_operands (rtx *);
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@ -13737,6 +13737,24 @@ neon_vector_mem_operand (rtx op, int type, bool strict)
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return FALSE;
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}
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/* Return TRUE if OP is a mem suitable for loading/storing an MVE struct
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type. */
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int
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mve_struct_mem_operand (rtx op)
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{
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rtx ind = XEXP (op, 0);
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/* Match: (mem (reg)). */
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if (REG_P (ind))
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return arm_address_register_rtx_p (ind, 0);
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/* Allow only post-increment by the mode size. */
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if (GET_CODE (ind) == POST_INC)
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return arm_address_register_rtx_p (XEXP (ind, 0), 0);
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return FALSE;
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}
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/* Return TRUE if OP is a mem suitable for loading/storing a Neon struct
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type. */
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int
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@ -474,6 +474,11 @@
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(and (match_code "mem")
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(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
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(define_memory_constraint "Ug"
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"@internal
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In Thumb-2 state a valid MVE struct load/store address."
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(match_operand 0 "mve_struct_operand"))
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(define_memory_constraint "Uj"
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"@internal
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In ARM/Thumb-2 state a VFP load/store address that supports writeback
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@ -99,7 +99,7 @@
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;; [vst4q])
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;;
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(define_insn "mve_vst4q<mode>"
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[(set (match_operand:XI 0 "neon_struct_operand" "=Um")
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[(set (match_operand:XI 0 "mve_struct_operand" "=Ug")
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(unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
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(unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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VST4Q))
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@ -9961,7 +9961,7 @@
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;; [vst2q])
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;;
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(define_insn "mve_vst2q<mode>"
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[(set (match_operand:OI 0 "neon_struct_operand" "=Um")
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[(set (match_operand:OI 0 "mve_struct_operand" "=Ug")
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(unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
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(unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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VST2Q))
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@ -9990,7 +9990,7 @@
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;;
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(define_insn "mve_vld2q<mode>"
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[(set (match_operand:OI 0 "s_register_operand" "=w")
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(unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
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(unspec:OI [(match_operand:OI 1 "mve_struct_operand" "Ug")
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(unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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VLD2Q))
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]
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@ -10018,7 +10018,7 @@
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;;
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(define_insn "mve_vld4q<mode>"
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[(set (match_operand:XI 0 "s_register_operand" "=w")
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(unspec:XI [(match_operand:XI 1 "neon_struct_operand" "Um")
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(unspec:XI [(match_operand:XI 1 "mve_struct_operand" "Ug")
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(unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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VLD4Q))
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]
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@ -876,6 +876,10 @@
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(and (match_code "mem")
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(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
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(define_predicate "mve_struct_operand"
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(and (match_code "mem")
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(match_test "TARGET_HAVE_MVE && mve_struct_mem_operand (op)")))
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(define_predicate "neon_permissive_struct_operand"
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(and (match_code "mem")
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(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)")))
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@ -0,0 +1,300 @@
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/* { dg-require-effective-target arm_v8_1m_mve_ok } */
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/* { dg-add-options arm_v8_1m_mve } */
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/* { dg-additional-options "-O1" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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#include "arm_mve.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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**test:
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** ...
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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*/
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void
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test(const uint8_t * in, uint8_t * out, int width)
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{
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uint8x16x2_t rg = vld2q(in);
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uint8x16x2_t gb = vld2q(in + width);
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vst2q (out, rg);
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vst2q (out + width, gb);
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}
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/*
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**test2:
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** ...
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]!
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]!
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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*/
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void
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test2(const uint8_t * in, uint8_t * out)
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{
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uint8x16x2_t rg = vld2q(in);
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uint8x16x2_t gb = vld2q(in + 32);
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vst2q (out, rg);
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vst2q (out + 32, gb);
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}
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/*
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**test3:
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** ...
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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*/
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void
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test3(const uint8_t * in, uint8_t * out)
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{
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uint8x16x2_t rg = vld2q(in);
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uint8x16x2_t gb = vld2q(in - 32);
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vst2q (out, rg);
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vst2q (out - 32, gb);
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}
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/*
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**test4:
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** ...
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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*/
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void
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test4(const uint8_t * in, uint8_t * out)
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{
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uint8x16x2_t rg = vld2q(in);
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uint8x16x2_t gb = vld2q(in + 64);
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vst2q (out, rg);
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vst2q (out + 64, gb);
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}
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/*
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**test5:
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** ...
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vld20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst20.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst21.8 {q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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*/
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void
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test5(const uint8_t * in, uint8_t * out)
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{
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uint8x16x2_t rg = vld2q(in);
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uint8x16x2_t gb = vld2q(in + 42);
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vst2q (out, rg);
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vst2q (out + 42, gb);
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}
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/*
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**test6:
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** ...
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** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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*/
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void
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test6(const uint8_t * in, uint8_t * out, int width)
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{
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uint8x16x4_t rg = vld4q(in);
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uint8x16x4_t gb = vld4q(in + width);
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vst4q (out, rg);
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vst4q (out + width, gb);
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}
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/*
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**test7:
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** ...
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** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** ...
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*/
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void
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test7(const uint8_t * in, uint8_t * out)
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{
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uint8x16x4_t rg = vld4q(in);
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uint8x16x4_t gb = vld4q(in + 32);
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vst4q (out, rg);
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vst4q (out + 32, gb);
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}
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/*
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**test8:
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** ...
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** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
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** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]!
|
||||
** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]!
|
||||
** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** ...
|
||||
*/
|
||||
void
|
||||
test8(const uint8_t * in, uint8_t * out)
|
||||
{
|
||||
uint8x16x4_t rg = vld4q(in);
|
||||
uint8x16x4_t gb = vld4q(in + 64);
|
||||
vst4q (out, rg);
|
||||
vst4q (out + 64, gb);
|
||||
}
|
||||
|
||||
/*
|
||||
**test9:
|
||||
** ...
|
||||
** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** ...
|
||||
** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** ...
|
||||
** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** ...
|
||||
** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** ...
|
||||
*/
|
||||
void
|
||||
test9(const uint8_t * in, uint8_t * out)
|
||||
{
|
||||
uint8x16x4_t rg = vld4q(in);
|
||||
uint8x16x4_t gb = vld4q(in - 64);
|
||||
vst4q (out, rg);
|
||||
vst4q (out - 64, gb);
|
||||
}
|
||||
|
||||
/*
|
||||
**test10:
|
||||
** ...
|
||||
** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** ...
|
||||
** vld40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vld43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** ...
|
||||
** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** ...
|
||||
** vst40.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst41.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst42.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** vst43.8 {q[0-9]+, q[0-9]+, q[0-9]+, q[0-9]+}, \[(?:ip|fp|r[0-9]+)\]
|
||||
** ...
|
||||
*/
|
||||
void
|
||||
test10(const uint8_t * in, uint8_t * out)
|
||||
{
|
||||
uint8x16x4_t rg = vld4q(in);
|
||||
uint8x16x4_t gb = vld4q(in + 42);
|
||||
vst4q (out, rg);
|
||||
vst4q (out + 42, gb);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
|
||||
Loading…
Add table
Reference in a new issue