From 41f42d120c4a6643f2f54952c180847d03405e3b Mon Sep 17 00:00:00 2001
From: Jiufu Guo <guojiufu@linux.ibm.com>
Date: Sat, 8 Oct 2022 12:57:51 +0800
Subject: [PATCH] rs6000: Enable const_anchor for 'addi'

There is a functionality as const_anchor in cse.cc.  This const_anchor
supports to generate new constants through adding small gap/offsets to
existing constant.  For example:

void __attribute__ ((noinline)) foo (long long *a)
{
  *a++ = 0x2351847027482577LL;
  *a++ = 0x2351847027482578LL;
}
The second constant (0x2351847027482578LL) can be compated by adding '1'
to the first constant (0x2351847027482577LL).
This is profitable if more than one instructions are need to build the
second constant.

* For rs6000, we can enable this functionality, as the instruction
'addi' is just for this when gap is smaller than 0x8000.

* One potential side effect of this feature:
Comparing with
"r101=0x2351847027482577LL
...
r201=0x2351847027482578LL"
The new r201 will be "r201=r101+1", and then r101 will live longer,
and would increase pressure when allocating registers.
But I feel, this would be acceptable for this const_anchor feature.

With this feature, for GCC source code and SPEC object files, the
significant changes are the improvement that: "addi" vs. "2 or more
insns: lis+or.."; it also exposes some other optimizations
opportunities: like combine/jump2. While the side effect is also
occurring in few cases, but it does not impact overall performance.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (TARGET_CONST_ANCHOR): New define.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/const_anchors.c: New test.
	* gcc.target/powerpc/try_const_anchors_ice.c: New test.
---
 gcc/config/rs6000/rs6000.cc                   |  4 ++++
 .../gcc.target/powerpc/const_anchors.c        | 20 +++++++++++++++++++
 .../powerpc/try_const_anchors_ice.c           | 16 +++++++++++++++
 3 files changed, 40 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/const_anchors.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ea68ca6faef..546c353029b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1760,6 +1760,10 @@ static const struct attribute_spec rs6000_attribute_table[] =
 
 #undef TARGET_UPDATE_IPA_FN_TARGET_INFO
 #define TARGET_UPDATE_IPA_FN_TARGET_INFO rs6000_update_ipa_fn_target_info
+
+#undef TARGET_CONST_ANCHOR
+#define TARGET_CONST_ANCHOR 0x8000
+
 
 
 /* Processor table.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/const_anchors.c b/gcc/testsuite/gcc.target/powerpc/const_anchors.c
new file mode 100644
index 00000000000..542e2674b12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/const_anchors.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target has_arch_ppc64 } } */
+/* { dg-options "-O2" } */
+
+#define C1 0x2351847027482577ULL
+#define C2 0x2351847027482578ULL
+
+void __attribute__ ((noinline)) foo (long long *a)
+{
+  *a++ = C1;
+  *a++ = C2;
+}
+
+void __attribute__ ((noinline)) foo1 (long long *a, long long b)
+{
+  *a++ = C1;
+  if (b)
+    *a++ = C2;
+}
+
+/* { dg-final { scan-assembler-times {\maddi\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c
new file mode 100644
index 00000000000..565b75a8279
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* __builtin_stack_restore could generates {[%1:DI]=0;} in BLK mode,
+   it could assert in try_const_anchors which only accepts SCALAR_INT.  */
+
+long
+foo (const int val)
+{
+  if (val == (0))
+    return 0;
+  void *p = __builtin_stack_save ();
+  char c = val;
+  __builtin_stack_restore (p);
+  return c;
+}