From 40571d67835ef8e9a3cf8815faed5d40caa5ff1b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 10 Jan 2002 19:47:24 -0800 Subject: [PATCH] alpha.c (print_operand): Add 'J'. * config/alpha/alpha.c (print_operand): Add 'J'. * config/alpha/alpha.md (call_osf_1_er, call_value_osf_1_er): Take a new operand with the sequence number for the lituse. When splitting the insns, use gen_movdi_er_high_g and generate a sequence number. (gen_movdi_er_high_g): Print the sequence number if non-zero. From-SVN: r48763 --- gcc/ChangeLog | 8 ++++++ gcc/config/alpha/alpha.c | 10 ++++++++ gcc/config/alpha/alpha.md | 51 ++++++++++++++++++++++++++++----------- 3 files changed, 55 insertions(+), 14 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 595f7f70de2..444c9e0187a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2002-01-10 Richard Henderson + + * config/alpha/alpha.c (print_operand): Add 'J'. + * config/alpha/alpha.md (call_osf_1_er, call_value_osf_1_er): Take a + new operand with the sequence number for the lituse. When splitting + the insns, use gen_movdi_er_high_g and generate a sequence number. + (gen_movdi_er_high_g): Print the sequence number if non-zero. + 2002-01-10 Aldy Hernandez * config/rs6000/rs6000.c (altivec_init_builtins): Add support for diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 8790e7d1137..71c59a6df3e 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -5136,6 +5136,16 @@ print_operand (file, x, code) output_operand_lossage ("invalid %%H value"); break; + case 'J': + if (GET_CODE (x) == CONST_INT) + { + if (INTVAL (x) != 0) + fprintf (file, "\t\t!lituse_jsr!%d", (int) INTVAL (x)); + } + else + output_operand_lossage ("invalid %%J value"); + break; + case 'r': /* If this operand is the constant zero, write it as "$31". */ if (GET_CODE (x) == REG) diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 9494e11ef83..fe256b6c415 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -4835,17 +4835,21 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_dup 1)) (set (reg:DI 26) (plus:DI (pc) (const_int 4))) (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) - (use (match_dup 0))])] + (use (match_dup 0)) + (use (match_dup 3))])] { if (CONSTANT_P (operands[0])) { operands[2] = gen_rtx_REG (Pmode, 27); - emit_move_insn (operands[2], operands[0]); + operands[3] = GEN_INT (alpha_next_sequence_number++); + emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, + operands[0], operands[3])); } else { operands[2] = operands[0]; operands[0] = const0_rtx; + operands[3] = const0_rtx; } }) @@ -4861,7 +4865,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_dup 1)) (set (reg:DI 26) (plus:DI (pc) (const_int 4))) (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) - (use (match_dup 0))]) + (use (match_dup 0)) + (use (match_dup 4))]) (set (reg:DI 29) (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1)) (set (reg:DI 29) @@ -4870,12 +4875,15 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" if (CONSTANT_P (operands[0])) { operands[2] = gen_rtx_REG (Pmode, 27); - emit_move_insn (operands[2], operands[0]); + operands[4] = GEN_INT (alpha_next_sequence_number++); + emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, + operands[0], operands[4])); } else { operands[2] = operands[0]; operands[0] = const0_rtx; + operands[4] = const0_rtx; } operands[3] = GEN_INT (alpha_next_sequence_number++); }) @@ -4888,9 +4896,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand 1 "" "")) (set (reg:DI 26) (plus:DI (pc) (const_int 4))) (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) - (use (match_operand 2 "" ""))] + (use (match_operand 2 "" "")) + (use (match_operand 3 "const_int_operand" ""))] "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" - "jsr $26,(%0),%2" + "jsr $26,(%0),%2%J3" [(set_attr "type" "jsr")]) (define_insn "*call_osf_1_noreturn" @@ -5495,14 +5504,19 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (match_dup 0) (match_dup 1))] "operands[1] = split_small_symbolic_mem_operand (operands[1]);") -(define_insn "*movdi_er_high_g" +(define_insn "movdi_er_high_g" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "global_symbolic_operand" "") (match_operand 3 "const_int_operand" "")] UNSPEC_LITERAL))] "TARGET_EXPLICIT_RELOCS" - "ldq %0,%2(%1)\t\t!literal" +{ + if (INTVAL (operands[3]) == 0) + return "ldq %0,%2(%1)\t\t!literal"; + else + return "ldq %0,%2(%1)\t\t!literal!%3"; +} [(set_attr "type" "ldsym")]) (define_split @@ -6891,17 +6905,21 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_dup 2))) (set (reg:DI 26) (plus:DI (pc) (const_int 4))) (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) - (use (match_dup 1))])] + (use (match_dup 1)) + (use (match_dup 4))])] { if (CONSTANT_P (operands[1])) { operands[3] = gen_rtx_REG (Pmode, 27); - emit_move_insn (operands[3], operands[1]); + operands[4] = GEN_INT (alpha_next_sequence_number++); + emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, + operands[1], operands[4])); } else { operands[3] = operands[1]; operands[1] = const0_rtx; + operands[4] = const0_rtx; } }) @@ -6919,7 +6937,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_dup 2))) (set (reg:DI 26) (plus:DI (pc) (const_int 4))) (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) - (use (match_dup 1))]) + (use (match_dup 1)) + (use (match_dup 5))]) (set (reg:DI 29) (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1)) (set (reg:DI 29) @@ -6928,12 +6947,15 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" if (CONSTANT_P (operands[1])) { operands[3] = gen_rtx_REG (Pmode, 27); - emit_move_insn (operands[3], operands[1]); + operands[5] = GEN_INT (alpha_next_sequence_number++); + emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, + operands[1], operands[5])); } else { operands[3] = operands[1]; operands[1] = const0_rtx; + operands[5] = const0_rtx; } operands[4] = GEN_INT (alpha_next_sequence_number++); }) @@ -6947,9 +6969,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (set (reg:DI 26) (plus:DI (pc) (const_int 4))) (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) - (use (match_operand 3 "" ""))] + (use (match_operand 3 "" "")) + (use (match_operand 4 "const_int_operand" ""))] "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" - "jsr $26,(%1),%3" + "jsr $26,(%1),%3%J4" [(set_attr "type" "jsr")]) (define_insn "*call_value_osf_1_noreturn"