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[AArch64 obvious] Fix register constraints for aarch64_ml[as]_elt_merge<mode>

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The MLA by-element instructions have the same restriction as other by-element
instructions whereby the forms operating on vectors of 16-bit integer data
may only use registers v0-v15. We have an iterator for that, applied to the
other patterns generating this instruction, so use that.

gcc/

	* config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): Fix
	register constraint for by-element operand.
	(aarch64_mls_elt_merge<mode>): Likewise.

From-SVN: r251568
This commit is contained in:
James Greenhalgh 2017-08-31 16:03:09 +00:00 • committed by James Greenhalgh
parent b54d4018b1
commit 3ec5b5f015
2 changed files with 8 additions and 2 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2017-08-31 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): Fix
register constraint for by-element operand.
(aarch64_mls_elt_merge<mode>): Likewise.
2017-08-31 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_can_follow_jump): Check for short

4
gcc/config/aarch64/aarch64-simd.md
View file

@ -1072,7 +1072,7 @@
[(set (match_operand:VDQHS 0 "register_operand" "=w")
(plus:VDQHS
(mult:VDQHS (vec_duplicate:VDQHS
(match_operand:<VEL> 1 "register_operand" "w"))
(match_operand:<VEL> 1 "register_operand" "<h_con>"))
(match_operand:VDQHS 2 "register_operand" "w"))
(match_operand:VDQHS 3 "register_operand" "0")))]
"TARGET_SIMD"
@ -1132,7 +1132,7 @@
(minus:VDQHS
(match_operand:VDQHS 1 "register_operand" "0")
(mult:VDQHS (vec_duplicate:VDQHS
(match_operand:<VEL> 2 "register_operand" "w"))
(match_operand:<VEL> 2 "register_operand" "<h_con>"))
(match_operand:VDQHS 3 "register_operand" "w"))))]
"TARGET_SIMD"
"mls\t%0.<Vtype>, %3.<Vtype>, %2.<Vetype>[0]"