Sub-dword vector extend and truncate for amdgcn
2019-12-13 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (sdwa): New mode attribute. (VCVT_FROM_MODE): Rename to ... (VCVT_MODE): ... this. (VCVT_TO_MODE): Delete mode iterator. (VCVT_FMODE): New mode iterator. (VCVT_IMODE): Likewise. (<cvt_name><VCVT_FROM_MODE:mode><VCVT_TO_MODE:mode>2<exec>): Change ... (<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): ... to this. (<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): New. (zero_convert): New code iterator. (convop): New code attribute. (<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>) : New. (extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>) : New. (vec_truncatev64div64si): Rename to ... (truncv64di<mode>2): ... this and implement sub-dword patterns. (vec_truncatev64div64si_exec): Rename to ... (truncv64di<mode>2_exec): ... this and implement sub-dword patterns. (<convop><mode>v64di2): New insn_and_split. (<convop><mode>v64di2_exec): Likewise. (mask_gather_load<mode>): Update truncate names. (mask_scatter_store<mode>): Likewise. * config/gcn/gcn.c (gcn_expand_scaled_offsets): Update truncate names. From-SVN: r279372
This commit is contained in:
Andrew Stubbs
Andrew Stubbs
parent
a93e1d5c70
commit
3d66c77719
3 changed files with 170 additions and 35 deletions
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@ -1,3 +1,30 @@
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2019-12-13 Andrew Stubbs <ams@codesourcery.com>
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* config/gcn/gcn-valu.md (sdwa): New mode attribute.
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(VCVT_FROM_MODE): Rename to ...
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(VCVT_MODE): ... this.
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(VCVT_TO_MODE): Delete mode iterator.
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(VCVT_FMODE): New mode iterator.
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(VCVT_IMODE): Likewise.
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(<cvt_name><VCVT_FROM_MODE:mode><VCVT_TO_MODE:mode>2<exec>): Change ...
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(<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): ... to this.
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(<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): New.
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(zero_convert): New code iterator.
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(convop): New code attribute.
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(<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>)
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: New.
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(extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>)
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: New.
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(vec_truncatev64div64si): Rename to ...
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(truncv64di<mode>2): ... this and implement sub-dword patterns.
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(vec_truncatev64div64si_exec): Rename to ...
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(truncv64di<mode>2_exec): ... this and implement sub-dword patterns.
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(<convop><mode>v64di2): New insn_and_split.
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(<convop><mode>v64di2_exec): Likewise.
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(mask_gather_load<mode>): Update truncate names.
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(mask_scatter_store<mode>): Likewise.
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* config/gcn/gcn.c (gcn_expand_scaled_offsets): Update truncate names.
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2019-12-13 Dennis Zhang <dennis.zhang@arm.com>
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* config/aarch64/aarch64-arches.def (armv8.6-a): New.
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@ -53,6 +53,8 @@
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[(V64QI "QI") (V64HI "HI") (V64SI "SI")
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(V64HF "HF") (V64SF "SF") (V64DI "DI") (V64DF "DF")])
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(define_mode_attr sdwa [(V64QI "BYTE_0") (V64HI "WORD_0") (V64SI "DWORD")])
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;; }}}
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;; {{{ Substitutions
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@ -2392,8 +2394,9 @@
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(define_mode_iterator CVT_FROM_MODE [HI SI HF SF DF])
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(define_mode_iterator CVT_TO_MODE [HI SI HF SF DF])
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(define_mode_iterator VCVT_FROM_MODE [V64HI V64SI V64HF V64SF V64DF])
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(define_mode_iterator VCVT_TO_MODE [V64HI V64SI V64HF V64SF V64DF])
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(define_mode_iterator VCVT_MODE [V64HI V64SI V64HF V64SF V64DF])
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(define_mode_iterator VCVT_FMODE [V64HF V64SF V64DF])
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(define_mode_iterator VCVT_IMODE [V64HI V64SI])
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(define_code_iterator cvt_op [fix unsigned_fix
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float unsigned_float
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@ -2416,11 +2419,21 @@
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[(set_attr "type" "vop1")
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(set_attr "length" "8")])
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(define_insn "<cvt_name><VCVT_FROM_MODE:mode><VCVT_TO_MODE:mode>2<exec>"
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[(set (match_operand:VCVT_TO_MODE 0 "register_operand" "= v")
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(cvt_op:VCVT_TO_MODE
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(match_operand:VCVT_FROM_MODE 1 "gcn_alu_operand" "vSvB")))]
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"gcn_valid_cvt_p (<VCVT_FROM_MODE:MODE>mode, <VCVT_TO_MODE:MODE>mode,
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(define_insn "<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>"
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[(set (match_operand:VCVT_FMODE 0 "register_operand" "= v")
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(cvt_op:VCVT_FMODE
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(match_operand:VCVT_MODE 1 "gcn_alu_operand" "vSvB")))]
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"gcn_valid_cvt_p (<VCVT_MODE:MODE>mode, <VCVT_FMODE:MODE>mode,
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<cvt_name>_cvt)"
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"v_cvt<cvt_operands>\t%0, %1"
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[(set_attr "type" "vop1")
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(set_attr "length" "8")])
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(define_insn "<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>"
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[(set (match_operand:VCVT_IMODE 0 "register_operand" "= v")
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(cvt_op:VCVT_IMODE
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(match_operand:VCVT_FMODE 1 "gcn_alu_operand" "vSvB")))]
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"gcn_valid_cvt_p (<VCVT_FMODE:MODE>mode, <VCVT_IMODE:MODE>mode,
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<cvt_name>_cvt)"
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"v_cvt<cvt_operands>\t%0, %1"
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[(set_attr "type" "vop1")
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@ -2429,42 +2442,137 @@
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;; }}}
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;; {{{ Int/int conversions
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(define_code_iterator zero_convert [truncate zero_extend])
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(define_code_attr convop [
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(sign_extend "extend")
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(zero_extend "zero_extend")
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(truncate "trunc")])
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(define_insn "<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>"
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[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
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(zero_convert:VEC_ALL1REG_INT_MODE
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(match_operand:VEC_ALL1REG_INT_ALT 1 "register_operand" " v")))]
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""
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"v_mov_b32_sdwa\t%0, %1 dst_sel:<VEC_ALL1REG_INT_MODE:sdwa> dst_unused:UNUSED_PAD src0_sel:<VEC_ALL1REG_INT_ALT:sdwa>"
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[(set_attr "type" "vop_sdwa")
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(set_attr "length" "8")])
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(define_insn "extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>"
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[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
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(sign_extend:VEC_ALL1REG_INT_MODE
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(match_operand:VEC_ALL1REG_INT_ALT 1 "register_operand" " v")))]
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""
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"v_mov_b32_sdwa\t%0, sext(%1) src0_sel:<VEC_ALL1REG_INT_ALT:sdwa>"
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[(set_attr "type" "vop_sdwa")
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(set_attr "length" "8")])
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;; GCC can already do these for scalar types, but not for vector types.
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;; Unfortunately you can't just do SUBREG on a vector to select the low part,
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;; so there must be a few tricks here.
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(define_insn_and_split "vec_truncatev64div64si"
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[(set (match_operand:V64SI 0 "register_operand" "=v,&v")
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(truncate:V64SI
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(match_operand:V64DI 1 "register_operand" " 0, v")))]
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(define_insn_and_split "truncv64di<mode>2"
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[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
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(truncate:VEC_ALL1REG_INT_MODE
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(match_operand:V64DI 1 "register_operand" " v")))]
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""
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"#"
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"reload_completed"
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[(set (match_dup 0) (match_dup 1))]
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[(const_int 0)]
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{
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operands[1] = gcn_operand_part (V64SImode, operands[1], 0);
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}
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[(set_attr "type" "vop2")
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(set_attr "length" "0,4")])
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rtx inlo = gcn_operand_part (V64DImode, operands[1], 0);
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rtx out = operands[0];
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(define_insn_and_split "vec_truncatev64div64si_exec"
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[(set (match_operand:V64SI 0 "register_operand" "=v,&v")
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(vec_merge:V64SI
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(truncate:V64SI
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(match_operand:V64DI 1 "register_operand" " 0, v"))
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(match_operand:V64SI 2 "gcn_alu_or_unspec_operand" "U0,U0")
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(match_operand:DI 3 "gcn_exec_operand" " e, e")))]
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if (<MODE>mode != V64SImode)
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emit_insn (gen_truncv64si<mode>2 (out, inlo));
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else
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emit_move_insn (out, inlo);
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}
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[(set_attr "type" "vop2")
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(set_attr "length" "4")])
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(define_insn_and_split "truncv64di<mode>2_exec"
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[(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
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(vec_merge:VEC_ALL1REG_INT_MODE
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(truncate:VEC_ALL1REG_INT_MODE
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(match_operand:V64DI 1 "register_operand" " v"))
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(match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_or_unspec_operand"
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"U0")
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(match_operand:DI 3 "gcn_exec_operand" " e")))]
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""
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"#"
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"reload_completed"
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[(parallel [(set (match_dup 0)
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(vec_merge:V64SI (match_dup 1) (match_dup 2) (match_dup 3)))
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(clobber (scratch:V64DI))])]
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[(const_int 0)]
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{
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operands[1] = gcn_operand_part (V64SImode, operands[1], 0);
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rtx out = operands[0];
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rtx inlo = gcn_operand_part (V64DImode, operands[1], 0);
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rtx merge = operands[2];
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rtx exec = operands[3];
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if (<MODE>mode != V64SImode)
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emit_insn (gen_truncv64si<mode>2_exec (out, inlo, merge, exec));
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else
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emit_insn (gen_mov<mode>_exec (out, inlo, exec, merge));
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}
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[(set_attr "type" "vop2")
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(set_attr "length" "0,4")])
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(set_attr "length" "4")])
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(define_insn_and_split "<convop><mode>v64di2"
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[(set (match_operand:V64DI 0 "register_operand" "=v")
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(any_extend:V64DI
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(match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v")))]
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""
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"#"
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"reload_completed"
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[(const_int 0)]
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{
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rtx outlo = gcn_operand_part (V64DImode, operands[0], 0);
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rtx outhi = gcn_operand_part (V64DImode, operands[0], 1);
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rtx in = operands[1];
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if (<MODE>mode != V64SImode)
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emit_insn (gen_<convop><mode>v64si2 (outlo, in));
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else
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emit_move_insn (outlo, in);
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if ('<su>' == 's')
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emit_insn (gen_ashrv64si3 (outhi, outlo, GEN_INT (31)));
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else
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emit_insn (gen_vec_duplicatev64si (outhi, const0_rtx));
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}
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[(set_attr "type" "mult")
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(set_attr "length" "12")])
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(define_insn_and_split "<convop><mode>v64di2_exec"
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[(set (match_operand:V64DI 0 "register_operand" "=v")
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(vec_merge:V64DI
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(any_extend:V64DI
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(match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v"))
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(match_operand:V64DI 2 "gcn_alu_or_unspec_operand" "U0")
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(match_operand:DI 3 "gcn_exec_operand" " e")))]
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""
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"#"
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"reload_completed"
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[(const_int 0)]
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{
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rtx outlo = gcn_operand_part (V64DImode, operands[0], 0);
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rtx outhi = gcn_operand_part (V64DImode, operands[0], 1);
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rtx in = operands[1];
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rtx mergelo = gcn_operand_part (V64DImode, operands[2], 0);
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rtx mergehi = gcn_operand_part (V64DImode, operands[2], 1);
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rtx exec = operands[3];
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if (<MODE>mode != V64SImode)
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emit_insn (gen_<convop><mode>v64si2_exec (outlo, in, mergelo, exec));
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else
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emit_insn (gen_mov<mode>_exec (outlo, in, exec, mergelo));
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if ('<su>' == 's')
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emit_insn (gen_ashrv64si3_exec (outhi, outlo, GEN_INT (31), mergehi,
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exec));
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else
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emit_insn (gen_vec_duplicatev64si_exec (outhi, const0_rtx, mergehi,
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exec));
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}
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[(set_attr "type" "mult")
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(set_attr "length" "12")])
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;; }}}
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;; {{{ Vector comparison/merge
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@ -2726,9 +2834,9 @@
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if (GET_MODE (operands[2]) == V64DImode)
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{
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rtx tmp = gen_reg_rtx (V64SImode);
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emit_insn (gen_vec_truncatev64div64si_exec (tmp, operands[2],
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gcn_gen_undef (V64SImode),
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exec));
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emit_insn (gen_truncv64div64si2_exec (tmp, operands[2],
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gcn_gen_undef (V64SImode),
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exec));
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operands[2] = tmp;
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}
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@ -2752,9 +2860,9 @@
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if (GET_MODE (operands[1]) == V64DImode)
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{
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rtx tmp = gen_reg_rtx (V64SImode);
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emit_insn (gen_vec_truncatev64div64si_exec (tmp, operands[1],
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gcn_gen_undef (V64SImode),
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exec));
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emit_insn (gen_truncv64div64si2_exec (tmp, operands[1],
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gcn_gen_undef (V64SImode),
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exec));
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operands[1] = tmp;
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}
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@ -1846,7 +1846,7 @@ gcn_expand_scaled_offsets (addr_space_t as, rtx base, rtx offsets, rtx scale,
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if (GET_MODE (offsets) == V64DImode)
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{
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rtx tmp = gen_reg_rtx (V64SImode);
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emit_insn (gen_vec_truncatev64div64si (tmp, offsets));
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emit_insn (gen_truncv64div64si2 (tmp, offsets));
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offsets = tmp;
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}
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