[GCC][PATCH][ARM]: Change arm constraint name from "e" to "Te".
This patches changes the constraint "e" to "Te". gcc/ChangeLog: 2020-04-24 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/constraints.md (e): Remove constraint. (Te): Define constraint. * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in operand 0 from "e" to "Te". (vaddvaq_<supf><mode>): Likewise. (vaddvq_p_<supf><mode>): Likewise. (vmladavq_<supf><mode>): Likewise. (vmladavxq_s<mode>): Likewise. (vmlsdavq_s<mode>): Likewise. (vmlsdavxq_s<mode>): Likewise. (vaddvaq_p_<supf><mode>): Likewise. (vmladavaq_<supf><mode>): Likewise. (vmladavq_p_<supf><mode>): Likewise. (vmladavxq_p_s<mode>): Likewise. (vmlsdavq_p_s<mode>): Likewise. (vmlsdavxq_p_s<mode>): Likewise. (vmlsdavaxq_s<mode>): Likewise. (vmlsdavaq_s<mode>): Likewise. (vmladavaxq_s<mode>): Likewise. (vmladavaq_p_<supf><mode>): Likewise. (vmladavaxq_p_s<mode>): Likewise. (vmlsdavaq_p_s<mode>): Likewise. (vmlsdavaxq_p_s<mode>): Likewise.
This commit is contained in:
Srinath Parvathaneni
parent
26d76be7af
commit
3d537943fb
3 changed files with 57 additions and 31 deletions
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@ -1,3 +1,29 @@
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2020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
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* config/arm/constraints.md (e): Remove constraint.
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(Te): Define constraint.
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* config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in
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operand 0 from "e" to "Te".
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(vaddvaq_<supf><mode>): Likewise.
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(vaddvq_p_<supf><mode>): Likewise.
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(vmladavq_<supf><mode>): Likewise.
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(vmladavxq_s<mode>): Likewise.
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(vmlsdavq_s<mode>): Likewise.
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(vmlsdavxq_s<mode>): Likewise.
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(vaddvaq_p_<supf><mode>): Likewise.
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(vmladavaq_<supf><mode>): Likewise.
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(vmladavq_p_<supf><mode>): Likewise.
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(vmladavxq_p_s<mode>): Likewise.
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(vmlsdavq_p_s<mode>): Likewise.
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(vmlsdavxq_p_s<mode>): Likewise.
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(vmlsdavaxq_s<mode>): Likewise.
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(vmlsdavaq_s<mode>): Likewise.
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(vmladavaxq_s<mode>): Likewise.
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(vmladavaq_p_<supf><mode>): Likewise.
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(vmladavaxq_p_s<mode>): Likewise.
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(vmlsdavaq_p_s<mode>): Likewise.
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(vmlsdavaxq_p_s<mode>): Likewise.
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2020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/arm/arm.c (output_move_neon): Only get the first operand if
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@ -32,7 +32,7 @@
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;; The following multi-letter normal constraints have been used:
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;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
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;; Dt, Dp, Dz, Tu
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;; Dt, Dp, Dz, Tu, Te
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;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
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;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb, Ra,
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;; Rg, Ri
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@ -50,8 +50,8 @@
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(define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS"
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"MVE FPCCR register")
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(define_register_constraint "e" "TARGET_HAVE_MVE ? EVEN_REG : NO_REGS"
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"MVE EVEN registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8},
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(define_register_constraint "Te" "TARGET_HAVE_MVE ? EVEN_REG : NO_REGS"
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"EVEN core registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8},
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@code{r10}, @code{r12}, @code{r14}")
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(define_constraint "Rd"
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@ -1102,7 +1102,7 @@
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;;
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(define_insn "mve_vaddvq_<supf><mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
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VADDVQ))
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]
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@ -1477,7 +1477,7 @@
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;;
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(define_insn "mve_vaddvaq_<supf><mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VADDVAQ))
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@ -1492,7 +1492,7 @@
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;;
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(define_insn "mve_vaddvq_p_<supf><mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:HI 2 "vpr_register_operand" "Up")]
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VADDVQ_P))
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@ -2032,7 +2032,7 @@
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;;
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(define_insn "mve_vmladavq_<supf><mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VMLADAVQ))
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@ -2047,7 +2047,7 @@
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;;
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(define_insn "mve_vmladavxq_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VMLADAVXQ_S))
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@ -2062,7 +2062,7 @@
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;;
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(define_insn "mve_vmlsdavq_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VMLSDAVQ_S))
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@ -2077,7 +2077,7 @@
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;;
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(define_insn "mve_vmlsdavxq_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VMLSDAVXQ_S))
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@ -3685,7 +3685,7 @@
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;;
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(define_insn "mve_vaddvaq_p_<supf><mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:HI 3 "vpr_register_operand" "Up")]
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@ -4101,7 +4101,7 @@
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;;
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(define_insn "mve_vmladavaq_<supf><mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:MVE_2 3 "s_register_operand" "w")]
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@ -4117,7 +4117,7 @@
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;;
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(define_insn "mve_vmladavq_p_<supf><mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:HI 3 "vpr_register_operand" "Up")]
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@ -4133,7 +4133,7 @@
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;;
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(define_insn "mve_vmladavxq_p_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:HI 3 "vpr_register_operand" "Up")]
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@ -4181,7 +4181,7 @@
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;;
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(define_insn "mve_vmlsdavq_p_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:HI 3 "vpr_register_operand" "Up")]
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@ -4197,7 +4197,7 @@
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;;
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(define_insn "mve_vmlsdavxq_p_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:HI 3 "vpr_register_operand" "Up")]
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@ -4581,7 +4581,7 @@
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;;
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(define_insn "mve_vmlsdavaxq_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:MVE_2 3 "s_register_operand" "w")]
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@ -4597,7 +4597,7 @@
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;;
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(define_insn "mve_vmlsdavaq_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:MVE_2 3 "s_register_operand" "w")]
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@ -4613,7 +4613,7 @@
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;;
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(define_insn "mve_vmladavaxq_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:MVE_2 3 "s_register_operand" "w")]
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@ -6298,7 +6298,7 @@
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;;
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(define_insn "mve_vmladavaq_p_<supf><mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:MVE_2 3 "s_register_operand" "w")
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@ -6808,7 +6808,7 @@
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;;
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(define_insn "mve_vmladavaxq_p_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:MVE_2 3 "s_register_operand" "w")
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@ -6825,7 +6825,7 @@
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;;
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(define_insn "mve_vmlsdavaq_p_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:MVE_2 3 "s_register_operand" "w")
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@ -6842,7 +6842,7 @@
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;;
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(define_insn "mve_vmlsdavaxq_p_s<mode>"
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[
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(set (match_operand:SI 0 "s_register_operand" "=e")
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(set (match_operand:SI 0 "s_register_operand" "=Te")
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(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
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(match_operand:MVE_2 2 "s_register_operand" "w")
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(match_operand:MVE_2 3 "s_register_operand" "w")
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@ -9736,7 +9736,7 @@
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(unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
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(match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
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VIDUPQ))
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(set (match_operand:SI 1 "s_register_operand" "=e")
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(set (match_operand:SI 1 "s_register_operand" "=Te")
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(plus:SI (match_dup 2)
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(match_operand:SI 4 "immediate_operand" "i")))]
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"TARGET_HAVE_MVE"
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@ -9772,7 +9772,7 @@
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(match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
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(match_operand:HI 5 "vpr_register_operand" "Up")]
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VIDUPQ_M))
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(set (match_operand:SI 2 "s_register_operand" "=e")
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(set (match_operand:SI 2 "s_register_operand" "=Te")
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(plus:SI (match_dup 3)
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(match_operand:SI 6 "immediate_operand" "i")))]
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"TARGET_HAVE_MVE"
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@ -9804,7 +9804,7 @@
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(unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
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(match_operand:SI 3 "immediate_operand" "i")]
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VDDUPQ))
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(set (match_operand:SI 1 "s_register_operand" "=e")
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(set (match_operand:SI 1 "s_register_operand" "=Te")
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(minus:SI (match_dup 2)
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(match_operand:SI 4 "immediate_operand" "i")))]
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"TARGET_HAVE_MVE"
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@ -9840,7 +9840,7 @@
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(match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
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(match_operand:HI 5 "vpr_register_operand" "Up")]
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VDDUPQ_M))
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(set (match_operand:SI 2 "s_register_operand" "=e")
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(set (match_operand:SI 2 "s_register_operand" "=Te")
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(minus:SI (match_dup 3)
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(match_operand:SI 6 "immediate_operand" "i")))]
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"TARGET_HAVE_MVE"
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@ -9891,7 +9891,7 @@
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(subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
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(match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
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VDWDUPQ))
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(set (match_operand:SI 1 "s_register_operand" "=e")
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(set (match_operand:SI 1 "s_register_operand" "=Te")
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(unspec:SI [(match_dup 2)
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(subreg:SI (match_dup 3) 4)
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(match_dup 4)]
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@ -9951,7 +9951,7 @@
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(match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
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(match_operand:HI 6 "vpr_register_operand" "Up")]
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VDWDUPQ_M))
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(set (match_operand:SI 1 "s_register_operand" "=e")
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(set (match_operand:SI 1 "s_register_operand" "=Te")
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(unspec:SI [(match_dup 2)
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(match_dup 3)
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(subreg:SI (match_dup 4) 4)
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@ -10008,7 +10008,7 @@
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(subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
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(match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
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VIWDUPQ))
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(set (match_operand:SI 1 "s_register_operand" "=e")
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(set (match_operand:SI 1 "s_register_operand" "=Te")
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(unspec:SI [(match_dup 2)
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(subreg:SI (match_dup 3) 4)
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(match_dup 4)]
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@ -10068,7 +10068,7 @@
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(match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
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(match_operand:HI 6 "vpr_register_operand" "Up")]
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VIWDUPQ_M))
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(set (match_operand:SI 1 "s_register_operand" "=e")
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(set (match_operand:SI 1 "s_register_operand" "=Te")
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(unspec:SI [(match_dup 2)
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(match_dup 3)
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(subreg:SI (match_dup 4) 4)
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Reference in a new issue