i386.h (TARGET_SAHF): New define.
* config/i386/i386.h (TARGET_SAHF): New define.
* config/i386/i386.c (ix86_tune_features) [X86_TUNE_USE_SAHF]:
Also enable for m_K8, m_AMDFAM10 and m_CORE2.
(x86_sahf): New global variable.
(override_options): Add PTA_NO_SAHF to pta_flags enum. Recode
pta_flags masks using shifts. Add PTA_NO_SAHF to x86_64 and
nocona processor flags. Set x86_sahf when PTA_NO_SAHF is not set
in processor flags. Do not unconditionally disable TARGET_USE_SAHF
for 64-bit.
(ix86_fp_comparison_sahf_cost): Return high value for !TARGET_SAHF.
(ix86_expand_fp_compare): Check for TARGET_CMOVE or TARGET_SAHF
when expanding fcomi/sahf based tests.
(ix86_emit_fp_unordered_jump): Check for TARGET_SAHF when
expanding sahf based alternative. Emit sahf based sequence when
optimizing for code size.
* config/i386/i386.md (x86_sahf_1): Do not disable for
TARGET_64BIT, enable for TARGET_SAHF.
From-SVN: r122705
This commit is contained in:
Uros Bizjak
parent
0c705abc64
commit
3c2d980c94
4 changed files with 62 additions and 32 deletions
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@ -1,3 +1,23 @@
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2007-03-08 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.h (TARGET_SAHF): New define.
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* config/i386/i386.c (ix86_tune_features) [X86_TUNE_USE_SAHF]:
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Also enable for m_K8, m_AMDFAM10 and m_CORE2.
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(x86_sahf): New global variable.
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(override_options): Add PTA_NO_SAHF to pta_flags enum. Recode
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pta_flags masks using shifts. Add PTA_NO_SAHF to x86_64 and
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nocona processor flags. Set x86_sahf when PTA_NO_SAHF is not set
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in processor flags. Do not unconditionally disable TARGET_USE_SAHF
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for 64-bit.
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(ix86_fp_comparison_sahf_cost): Return high value for !TARGET_SAHF.
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(ix86_expand_fp_compare): Check for TARGET_CMOVE or TARGET_SAHF
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when expanding fcomi/sahf based tests.
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(ix86_emit_fp_unordered_jump): Check for TARGET_SAHF when
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expanding sahf based alternative. Emit sahf based sequence when
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optimizing for code size.
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* config/i386/i386.md (x86_sahf_1): Do not disable for
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TARGET_64BIT, enable for TARGET_SAHF.
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2007-03-08 Martin Michlmayr <tbm@cyrius.com>
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* tree-ssa-coalesce.c (fail_abnormal_edge_coalesce): Remove
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@ -505,7 +525,7 @@
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of comparison of non-null ADDR_EXPR against null.
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2007-03-05 Richard Guenther <rguenther@suse.de>
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Dorit Nuzman <dorit@il.ibm.com>
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Dorit Nuzman <dorit@il.ibm.com>
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PR tree-optimization/26420
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* tree-vectorizer.c (vectorize_loops): Bail out early if there
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@ -515,9 +535,9 @@
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2007-03-05 Revital Eres <eres@il.ibm.com>
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* gcc.dg/var-expand1.c: New test.
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* loop-unroll.c (analyze_insn_to_expand_var): Add dump info
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when an accumulator is expanded.
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* gcc.dg/var-expand1.c: New test.
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* loop-unroll.c (analyze_insn_to_expand_var): Add dump info
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when an accumulator is expanded.
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2007-03-04 Manuel Lopez-Ibanez <manu@gcc.gnu.org>
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@ -1039,11 +1039,11 @@ unsigned int ix86_tune_features[X86_TUNE_LAST] = {
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~m_386,
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/* X86_TUNE_USE_SAHF */
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m_PPRO | m_K6_GEODE | m_PENT4 | m_NOCONA | m_GENERIC32,
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/* | m_GENERIC | m_ATHLON_K8 ? */
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m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
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| m_NOCONA | m_CORE2 | m_GENERIC32,
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/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
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partial dependencies */
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partial dependencies. */
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m_ATHLON_K8_AMDFAM10 | m_PPRO | m_PENT4 | m_NOCONA
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| m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
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@ -1441,6 +1441,11 @@ int x86_prefetch_sse;
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/* true if cmpxchg16b is supported. */
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int x86_cmpxchg16b;
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/* true if sahf is supported. Early Intel CPUs with Intel 64
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lacked LAHF and SAHF instructions supported by AMD64 until
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introduction of Pentium 4 G1 step in December 2005. */
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int x86_sahf;
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/* ix86_regparm_string as a number */
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static int ix86_regparm;
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@ -1884,19 +1889,20 @@ override_options (void)
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const enum processor_type processor;
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const enum pta_flags
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{
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PTA_SSE = 1,
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PTA_SSE2 = 2,
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PTA_SSE3 = 4,
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PTA_MMX = 8,
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PTA_PREFETCH_SSE = 16,
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PTA_3DNOW = 32,
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PTA_3DNOW_A = 64,
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PTA_64BIT = 128,
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PTA_SSSE3 = 256,
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PTA_CX16 = 512,
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PTA_POPCNT = 1024,
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PTA_ABM = 2048,
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PTA_SSE4A = 4096
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PTA_SSE = 1 << 0,
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PTA_SSE2 = 1 << 1,
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PTA_SSE3 = 1 << 2,
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PTA_MMX = 1 << 3,
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PTA_PREFETCH_SSE = 1 << 4,
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PTA_3DNOW = 1 << 5,
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PTA_3DNOW_A = 1 << 6,
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PTA_64BIT = 1 << 7,
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PTA_SSSE3 = 1 << 8,
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PTA_CX16 = 1 << 9,
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PTA_POPCNT = 1 << 10,
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PTA_ABM = 1 << 11,
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PTA_SSE4A = 1 << 12,
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PTA_NO_SAHF = 1 << 13
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} flags;
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}
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const processor_alias_table[] =
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@ -1923,7 +1929,8 @@ override_options (void)
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{"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_MMX | PTA_PREFETCH_SSE},
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{"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
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| PTA_MMX | PTA_PREFETCH_SSE | PTA_CX16},
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| PTA_MMX | PTA_PREFETCH_SSE
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| PTA_CX16 | PTA_NO_SAHF},
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{"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
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| PTA_64BIT | PTA_MMX
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| PTA_PREFETCH_SSE | PTA_CX16},
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@ -1943,7 +1950,7 @@ override_options (void)
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{"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
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| PTA_3DNOW_A | PTA_SSE},
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{"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
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| PTA_SSE | PTA_SSE2 },
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| PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
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{"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
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| PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
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{"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
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@ -2146,6 +2153,8 @@ override_options (void)
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if (processor_alias_table[i].flags & PTA_SSE4A
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&& !(target_flags_explicit & MASK_SSE4A))
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target_flags |= MASK_SSE4A;
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if (!(processor_alias_table[i].flags & PTA_NO_SAHF))
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x86_sahf = true;
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if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
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error ("CPU you selected does not support x86-64 "
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"instruction set");
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@ -2465,10 +2474,6 @@ override_options (void)
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if (TARGET_SSE)
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TARGET_CMOVE = 1;
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/* ??? Any idea why this is unconditionally disabled for 64-bit? */
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if (TARGET_64BIT)
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TARGET_USE_SAHF = 0;
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/* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
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{
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char *p;
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@ -10976,7 +10981,7 @@ ix86_fp_comparison_sahf_cost (enum rtx_code code)
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enum rtx_code bypass_code, first_code, second_code;
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/* Return arbitrarily high cost when instruction is not preferred - this
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avoids gcc from using it. */
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if (!TARGET_USE_SAHF && !optimize_size)
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if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
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return 1024;
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ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
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return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
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@ -11023,7 +11028,8 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
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ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
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/* Do fcomi/sahf based test when profitable. */
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if ((bypass_code == UNKNOWN || bypass_test)
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if ((TARGET_CMOVE || TARGET_SAHF)
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&& (bypass_code == UNKNOWN || bypass_test)
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&& (second_code == UNKNOWN || second_test)
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&& ix86_fp_comparison_arithmetics_cost (code) > cost)
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{
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@ -21007,7 +21013,7 @@ ix86_emit_fp_unordered_jump (rtx label)
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emit_insn (gen_x86_fnstsw_1 (reg));
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if (TARGET_USE_SAHF)
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if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
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{
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emit_insn (gen_x86_sahf_1 (reg));
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@ -191,7 +191,7 @@ enum ix86_tune_indices {
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X86_TUNE_DEEP_BRANCH_PREDICTION,
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X86_TUNE_BRANCH_PREDICTION_HINTS,
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X86_TUNE_DOUBLE_WITH_ADD,
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X86_TUNE_USE_SAHF, /* && !TARGET_64BIT */
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X86_TUNE_USE_SAHF,
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X86_TUNE_MOVX,
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X86_TUNE_PARTIAL_REG_STALL,
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X86_TUNE_PARTIAL_FLAG_REG_STALL,
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@ -330,6 +330,9 @@ extern int x86_prefetch_sse;
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extern int x86_cmpxchg16b;
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#define TARGET_CMPXCHG16B x86_cmpxchg16b
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extern int x86_sahf;
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#define TARGET_SAHF x86_sahf
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#define ASSEMBLER_DIALECT (ix86_asm_dialect)
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#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
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@ -983,8 +983,9 @@
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(define_insn "x86_sahf_1"
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[(set (reg:CC FLAGS_REG)
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(unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
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"!TARGET_64BIT"
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(unspec:CC [(match_operand:HI 0 "register_operand" "a")]
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UNSPEC_SAHF))]
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"TARGET_SAHF"
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"sahf"
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[(set_attr "length" "1")
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(set_attr "athlon_decode" "vector")
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Loading…
Add table
Reference in a new issue