ira: Scale save/restore costs of callee save registers with block frequency

In assign_hard_reg(), when computing the costs of the hard registers, the
cost of saving/restoring a callee-save hard register in prolog/epilog is
taken into consideration. However, this cost is not scaled with the entry
block frequency. Without scaling, the cost of saving/restoring is quite
small and this can result in a callee-save register being chosen by
assign_hard_reg() even though there are free caller-save registers
available. Assigning a callee save register to a pseudo that is live
in the entire function and across a call will cause shrink wrap to fail.

2024-06-25  Surya Kumari Jangala  <jskumari@linux.ibm.com>

gcc/
	PR rtl-optimization/111673
	* ira-color.cc (assign_hard_reg): Scale save/restore costs of
	callee save registers with block frequency.

gcc/testsuite/
	PR rtl-optimization/111673
	* gcc.target/powerpc/pr111673.c: New test.
This commit is contained in:
Surya Kumari Jangala 2024-06-25 08:37:49 -05:00
parent 9f168b412f
commit 3b9b8d6cfd
2 changed files with 20 additions and 1 deletions

View file

@ -2178,7 +2178,9 @@ assign_hard_reg (ira_allocno_t a, bool retry_p)
add_cost = ((ira_memory_move_cost[mode][rclass][0]
+ ira_memory_move_cost[mode][rclass][1])
* saved_nregs / hard_regno_nregs (hard_regno,
mode) - 1);
mode) - 1)
* (optimize_size ? 1 :
REG_FREQ_FROM_BB (ENTRY_BLOCK_PTR_FOR_FN (cfun)));
cost += add_cost;
full_cost += add_cost;
}

View file

@ -0,0 +1,17 @@
/* { dg-do compile { target lp64 } } */
/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue" } */
/* Verify there is an early return without the prolog and shrink-wrap
the function. */
int f (int);
int
advance (int dz)
{
if (dz > 0)
return (dz + dz) * dz;
else
return dz * f (dz);
}
/* { dg-final { scan-rtl-dump-times "Performing shrink-wrapping" 1 "pro_and_epilogue" } } */