rs6000: Rename 110 -> VSCR_REGNO
* config/rs6000/altivec.md: Use VSCR_REGNO instead of 110 throughout. From-SVN: r239948
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
95bde43a92
commit
3b2475ab31
2 changed files with 23 additions and 18 deletions
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@ -1,3 +1,7 @@
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2016-09-01 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/altivec.md: Use VSCR_REGNO instead of 110 throughout.
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2016-09-01 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/altivec.md: Use VRSAVE_REGNO instead of 109 throughout.
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@ -508,7 +508,7 @@
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(unspec:VI [(match_operand:VI 1 "register_operand" "v")
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(match_operand:VI 2 "register_operand" "v")]
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UNSPEC_VADDU))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"<VI_unit>"
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"vaddu<VI_char>s %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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@ -518,7 +518,7 @@
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(unspec:VI [(match_operand:VI 1 "register_operand" "v")
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(match_operand:VI 2 "register_operand" "v")]
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UNSPEC_VADDS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
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"vadds<VI_char>s %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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@ -554,7 +554,7 @@
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(unspec:VI [(match_operand:VI 1 "register_operand" "v")
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(match_operand:VI 2 "register_operand" "v")]
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UNSPEC_VSUBU))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
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"vsubu<VI_char>s %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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@ -564,7 +564,7 @@
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(unspec:VI [(match_operand:VI 1 "register_operand" "v")
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(match_operand:VI 2 "register_operand" "v")]
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UNSPEC_VSUBS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
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"vsubs<VI_char>s %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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@ -830,7 +830,7 @@
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(match_operand:V8HI 2 "register_operand" "v")
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(match_operand:V4SI 3 "register_operand" "v")]
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UNSPEC_VMSUMUHS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vmsumuhs %0,%1,%2,%3"
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[(set_attr "type" "veccomplex")])
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@ -841,7 +841,7 @@
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(match_operand:V8HI 2 "register_operand" "v")
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(match_operand:V4SI 3 "register_operand" "v")]
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UNSPEC_VMSUMSHS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vmsumshs %0,%1,%2,%3"
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[(set_attr "type" "veccomplex")])
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@ -902,7 +902,7 @@
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(match_operand:V8HI 2 "register_operand" "v")
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(match_operand:V8HI 3 "register_operand" "v")]
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UNSPEC_VMHADDSHS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vmhaddshs %0,%1,%2,%3"
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[(set_attr "type" "veccomplex")])
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@ -913,7 +913,7 @@
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(match_operand:V8HI 2 "register_operand" "v")
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(match_operand:V8HI 3 "register_operand" "v")]
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UNSPEC_VMHRADDSHS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vmhraddshs %0,%1,%2,%3"
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[(set_attr "type" "veccomplex")])
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@ -1699,7 +1699,7 @@
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(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
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(match_operand:V4SI 2 "register_operand" "v")]
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UNSPEC_VSUM4UBS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vsum4ubs %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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@ -1709,7 +1709,7 @@
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(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
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(match_operand:V4SI 2 "register_operand" "v")]
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UNSPEC_VSUM4S))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vsum4s<VI_char>s %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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@ -1722,7 +1722,7 @@
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
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(match_operand:V4SI 2 "register_operand" "v")]
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UNSPEC_VSUM2SWS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
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(clobber (match_scratch:V4SI 3 "=v"))]
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"TARGET_ALTIVEC"
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{
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@ -1743,7 +1743,7 @@
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
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(match_operand:V4SI 2 "register_operand" "v")]
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UNSPEC_VSUMSWS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
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(clobber (match_scratch:V4SI 3 "=v"))]
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"TARGET_ALTIVEC"
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{
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@ -1764,7 +1764,7 @@
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
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(match_operand:V4SI 2 "register_operand" "v")]
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UNSPEC_VSUMSWS_DIRECT))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vsumsws %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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@ -2124,7 +2124,7 @@
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(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
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(match_operand:QI 2 "immediate_operand" "i")]
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UNSPEC_VCTUXS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vctuxs %0,%1,%2"
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[(set_attr "type" "vecfloat")])
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@ -2134,7 +2134,7 @@
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(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
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(match_operand:QI 2 "immediate_operand" "i")]
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UNSPEC_VCTSXS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vctsxs %0,%1,%2"
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[(set_attr "type" "vecfloat")])
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@ -2359,7 +2359,7 @@
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[(set_attr "type" "veccmp")])
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(define_insn "altivec_mtvscr"
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[(set (reg:SI 110)
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[(set (reg:SI VSCR_REGNO)
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(unspec_volatile:SI
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[(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
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"TARGET_ALTIVEC"
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@ -2368,7 +2368,7 @@
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(define_insn "altivec_mfvscr"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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(unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
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(unspec_volatile:V8HI [(reg:SI VSCR_REGNO)] UNSPECV_MFVSCR))]
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"TARGET_ALTIVEC"
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"mfvscr %0"
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[(set_attr "type" "vecsimple")])
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@ -2757,7 +2757,8 @@
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(unspec:VI [(match_dup 2)
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(match_operand:VI 1 "register_operand" "v")]
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UNSPEC_VSUBS))
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(set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
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(set (reg:SI VSCR_REGNO)
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(unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
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(set (match_operand:VI 0 "register_operand" "=v")
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(smax:VI (match_dup 1) (match_dup 3)))]
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"TARGET_ALTIVEC"
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