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* config/xtensa/xtensa.c

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(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define.
	* xtensa.md: Replace the old pipeline description with a DFA model.

From-SVN: r83358
This commit is contained in:
Steven Bosscher 2004-06-18 19:38:27 +00:00 • committed by Steven Bosscher
parent ab3d88bed1
commit 3b1cce6ac1
3 changed files with 37 additions and 7 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2004-06-18 Steven Bosscher <stevenb@suse.de>
* config/xtensa/xtensa.c
(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define.
* xtensa.md: Replace the old pipeline description with a DFA model.
2004-06-18 Steven Bosscher <stevenb@suse.de>
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>

3
gcc/config/xtensa/xtensa.c
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@ -259,6 +259,9 @@ static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
#undef TARGET_RETURN_IN_MSB
#define TARGET_RETURN_IN_MSB xtensa_return_in_msb
#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
struct gcc_target targetm = TARGET_INITIALIZER;

35
gcc/config/xtensa/xtensa.md
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@ -52,20 +52,41 @@
[(set_attr "type" "multi")])
;; Functional units.
;; Pipeline model.
(define_function_unit "memory" 1 0 (eq_attr "type" "load,fload") 2 0)
;; The Xtensa basically has simple 5-stage RISC pipeline.
;; Most instructions complete in 1 cycle, and it is OK to assume that
;; everything is fully pipelined. The exceptions have special insn
;; reservations in the pipeline description below. The Xtensa can
;; issue one instruction per cycle, so defining CPU units is unnecessary.
(define_function_unit "sreg" 1 1 (eq_attr "type" "rsr") 2 0)
(define_insn_reservation "xtensa_any_insn" 1
(eq_attr "type" "!load,fload,rsr,mul16,mul32,fmadd,fconv")
"nothing")
(define_function_unit "mul16" 1 0 (eq_attr "type" "mul16") 2 0)
(define_insn_reservation "xtensa_memory" 2
(eq_attr "type" "load,fload")
"nothing")
(define_function_unit "mul32" 1 0 (eq_attr "type" "mul32") 2 0)
(define_insn_reservation "xtensa_sreg" 2
(eq_attr "type" "rsr")
"nothing")
(define_function_unit "fpmadd" 1 0 (eq_attr "type" "fmadd") 4 0)
(define_insn_reservation "xtensa_mul16" 2
(eq_attr "type" "mul16")
"nothing")
(define_function_unit "fpconv" 1 0 (eq_attr "type" "fconv") 2 0)
(define_insn_reservation "xtensa_mul32" 2
(eq_attr "type" "mul32")
"nothing")
(define_insn_reservation "xtensa_fmadd" 4
(eq_attr "type" "fmadd")
"nothing")
(define_insn_reservation "xtensa_fconv" 2
(eq_attr "type" "fconv")
"nothing")
;; Addition.